clk_div illigal connection

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Hi,

this is my code

    dcm1_1 : dcm1 port map (
        CLKIN_IN => CLK,
        RST_IN => RESET,
        CLKFX_OUT => clk_20M,
        CLKIN_IBUFG_OUT => open,
        CLK0_OUT => clk_int,
        LOCKED_OUT => locked);

    clk_div_1 : clk_div_262k
        port map (
            CLK => CLK_20M,
            DIV_262144 => clk_led2);

I get this error there during synthesis:
ERROR:Xst:2035 - Port <clk> has illegal connection. Port is connected to
input buffer and following ports:
    Port C of instance cnt1_1/BU20 in unit cnt1_1 with type FDE

I have no idea where the problem is.

Is it generally a good idea to use the dcm and a clk_divider if a very
slow frequency is needed? Or should I use only clk_dividers?

regards,
Benjamin

Re: clk_div illigal connection
Benjamin,

If you wish to use the CLKDV output, that uses the DLL part of the DCM,
and it requires CLK0 to CLKFB (for phase alignment feedback -- required
by using any of the CLK0, 90, 189, 270, 2X, or DV outputs), and a CLKIN
less than 24 MHz.

Since you are also using the CLKFX output at the same time, the M and D
values have to be such that with the CLKIN (which must be greater than
24 MHz since you used the CLKDV output), places the CLKFX output
frequency in an allowed range for either low, or high frequency modes.

If you have clock less than 24 MHz, and want a 20 MHz clock out, you
can't do that (even if you don't use CLKDV):  20 MHz is too slow an
output for the DFS part of the DCM (output must be greater than 24 MHz).
  I would instead go to a higher freqeuncy (in range), and divide it
down externally in the fabric.  There will be timing skews, etc. (since
you can't use the DCM for division, and are uising local routing for
clock signals) but at least you can make it work that way.

Austin

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