Hi,
when I use a CLK input-pin in vhdl in my top-level file, is this automatically the clk signal of my device? Or do I have to constrain it to the correct PIN?
regards, Benjamin
Hi,
when I use a CLK input-pin in vhdl in my top-level file, is this automatically the clk signal of my device? Or do I have to constrain it to the correct PIN?
regards, Benjamin
Hi,
I figured out that I have to do it. It works now. Thanks anyway :)
regards, Benjamin
Benjamin,
DesignF/X from
With best wishes, Manu Pillai
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