Field-Programmable Gate Arrays

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Problem with JTAG server on Quartus 4.0 for XP

Hello, I'am trying to use Quartus II and NIOS II sdk for teaching and I'm facing a problem with the JTAG server service...
0 comments posted 21yrs
posted by sderrienREMOVE
0 comments posted 21yrs posted by sderrienREMOVE

Map Error: "RLOC not supported for simple gates"

Hi, What do these MAP errors mean: WARNING:MapLib - Property RLOC on wrsel7 not supported for simple gates ignoring. WA...
3 comments posted 21yrs
posted by send_no_spam_to_jimgeorge
3 comments posted 21yrs posted by send_no_spam_to_jimgeorge

Gated Clock Timing

I am using VirtexE to communication with an ADI's chip. The interface include, write, read, Data, and Address. I wish F...
0 comments posted 21yrs
posted by fwj
0 comments posted 21yrs posted by fwj

How to implement this C function in FPGA

Dear Gurus, I've few concerns from the given function. 1. Do I necessary have to re-implement the data-type from float/...
7 comments posted 21yrs
posted by cltsaig
7 comments posted 21yrs posted by cltsaig

FPGA applications in RFID

We are looking for a Sr. Digital FPGA Engineer to work as a senior member of our RFID reader design team. Primary respo...
0 comments posted 21yrs
posted by gcarlson
0 comments posted 21yrs posted by gcarlson

crazy behaviour of fpga, timing ?

Hello, I use Quartus 4.2 SP1 WebEdition for my work. The Hardware I built gets data from an external source with 40Mbit...
12 comments posted 21yrs
posted by alexander.korff
12 comments posted 21yrs posted by alexander.korff

Xilinx FPU for Virtex-4 over FPU

I understand that Xilinx will be doing a Floating Point Unit that uses the APU interface. I haven't been able to find o...
1 comments posted 21yrs
posted by laguna_b1
1 comments posted 21yrs posted by laguna_b1

Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)

FYI: I found that it was necessary to unzip the self-extracting exe file for webpack 7.1 and then run 'wine setup.exe'....
4 comments posted 21yrs
posted by ptkwt
4 comments posted 21yrs posted by ptkwt

Flexray ip core

hello all, I'm looking for a Flexray IP core: Commercial or OpenSource project Flexray is a time triggered bus that aim...
3 comments posted 21yrs
posted by mouarf
3 comments posted 21yrs posted by mouarf

Formal verification tool?

Hello, Does anyone know of any freeware formal verification tool for verilog. Thanks MORPHEUS
0 comments posted 21yrs
posted by saurster
0 comments posted 21yrs posted by saurster

clk-pad, ibufg, dcm Problem

Hi, I have my clk from the pad connected to an ibufg like this: IBUFG_clk_main: IBUFG port map ( O => clk_main, -- Cloc...
2 comments posted 21yrs
posted by benjamin
2 comments posted 21yrs posted by benjamin

MIcroblaze FSL Datasheet

Hello I was looking in Google, but I wasnt able to find the datasheet for the FSL interface of the Microblaze interface...
1 comments posted 21yrs
posted by Patrick.Bateman23
1 comments posted 21yrs posted by Patrick.Bateman23

Change OCM Clock

Hi everyone !! Could anybody tell me how to change the On-Chip Memory clock frequency. I have the Power PC running at 3...
3 comments posted 21yrs
posted by johnsons
3 comments posted 21yrs posted by johnsons

Signal use from pin

Hi newsgroup, in my last post "SYNC + FIFO" I talked about the sychronization method of an external data stream. Additi...
2 comments posted 21yrs
posted by ALuPin
2 comments posted 21yrs posted by ALuPin

XPS vs. Project navigator

Chip : virtex 2 (microblaze) multimedia board company : xilinx Question : On my system i have 2 environments ... Xilinx...
0 comments posted 21yrs
posted by manmeetbhangu
0 comments posted 21yrs posted by manmeetbhangu