Change OCM Clock

Hi everyone !!

Could anybody tell me how to change the On-Chip Memory clock frequency. I have the Power PC running at 300MHz and the OCM at 100MHz. What all I did to double the OCM frequency was that I added the CLK2X port of the Digital Clock Module (DCM) and connect it to the powerpc port BRAMDSOCMCLK and the dsocm port DSOCM_Clk. Did I do any mistake, or is it something more that I need to do here!!

Well, I am using a Virtex II Pro device. I will add the relevant (changed) part of the MHS file here:

BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_DIVIDE = 1 PARAMETER C_CLKFX_MULTIPLY = 3 PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = proc_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock PORT CLK2X = dcm_0_CLK2X ########## WHAT I ADDED!! END

BEGIN dsocm_v10 PARAMETER INSTANCE = docm PARAMETER HW_VER = 2.00.a PARAMETER C_DSCNTLVALUE = 0x85 PORT DSOCM_Clk = dcm_0_CLK2X ### WHAT I CHANGED !! Before it was sys_clk_s PORT sys_rst = sys_bus_reset END

BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE DSOCM = docm BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT BRAMDSOCMCLK = dcm_0_CLK2X ##### WHAT I CHANGED !!Before it was sys_clk_s PORT CPMC405CLOCK = proc_clk_s END

Somebody please help !!!

Regards, Joe

Reply to
Joey
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Hi

In between, I forgot to mention something, I use VHDL. I have found something like, in Verilog, there is a file called global_params.v

"Joey" schrieb im Newsbeitrag news:d4qs07$t5p$ snipped-for-privacy@news.uni-kl.de...

to

sys_clk_s

Reply to
Joey

The relationship between the processor core and the OCM port needs to be an integer multiple. You cannot run the processor at 300 MHz and the OCM at 200MHz.

Valid combinations are 300/100 (what you have up and running), 300/150, or 200/200.

Don't forget to change PARAMETER C_DSCNTLVALUE to the correct value dependent on your clock settings.

- Peter

Joey wrote:

Reply to
Peter Ryser

If in the wizard it shows only 100MHz for Bus frequency when the CPU frequency is 300MHz. Do that mean I cannot increase the Bus frequency to

300MHz, in the .MHS file. The timing constraints document from Xilinx says that I can have the same CPU frequncy and the Bus frequency, as explained with the 1:1 frequency ratio

"Peter Ryser" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com...

I

did to

the

I

(changed)

sys_clk_s

Reply to
Joey

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