Map Error: "RLOC not supported for simple gates"

gates

simple

messes

The problem with attaching RLOC to a gate, even if the gate is instantiated rather than inferred, is that the mapper will not necessarily keep the gate by itself in the final design. Usually several gates can be lumped into a single LUT. The tools might have allowed an RLOC constraint on gates that don't get grouped together, but unfortunately they don't. If you have a combinatorial function that needs to end up with a particular placement, the only way is to instantiate a LUT instead of gates or gate primitives.

Instantiated flip-flops don't have this problem.

OK... thanks. I guess Xilinx has their reasons.

You can also use the xc_map attribute (synplify, although I think XST also added that attribute) if you put the gates into a separate entity and put the xc_map attribute on that entity.

--FMAP'd or2 library IEEE; use IEEE.std_logic_1164.all;

entity fmap_or2 is port ( a, b : in std_logic; z : out std_logic); end fmap_or2; architecture rtl of fmap_or2 is attribute xc_map : STRING; attribute xc_map of rtl : architecture is "lut"; attribute syn_hier: string; attribute syn_hier of rtl:architecture is "hard"; begin z