Hi newsgroup,
in my last post "SYNC + FIFO" I talked about the sychronization method of an external data stream. Additional to the bus data I have some control signals coming from the USB transceiver which are also synchronous to the RXCLK which I use as the FIFO write clock (see last post).
In order to respond directly to the control signals I get from the transceiver(for example: USB transceiver drives one control signal high to notify the FPGA to place the next data byte on the DATA[7..0] bus) I have to use the control signal from the pin in my state machine running with the RXCLK.
What recommendations do you make when using such a signal from a pin with regard to placement, timing constraints etc. ?
Thank you for your great help.
Rgds André