thanks for the answer Gabor. It seems that I have to do something inside the fpga to get it faster.
I experimented a little bit further and found out, that my limit is at
I am using a XC2VP4 with speedgrade 5.
The synthesize report says 240 MHz is the max clock for some nets, but these (listed) nets are not important. The important lvds_in_x nets are not listed there. Is it usefull to put a bufg on every line that goes into the obufds? At the moment these are just normal nets. (see the code attached).
At the moment I use a DCM to generate the 240 MHz. Then I use a process, to divide the clock by 7 and form the asymmetric clock. (see the code attached).
When I simulate my code in modelsim as Post-Map, everything looks okay. But when I do Post-Place & Route the clock lvds channel and the data channels are off by 1 lvds-clk cycle (I mean 1/240MHz), furthermore the lvds-data-channel with the DTMG (Data Pixel Enable) doesn't go high (on active) anymore, instead it becomes X for the high time. (However in Hardware it works.)
My goal is about 350-400 MHz.
Maybe I should set some contraints, what would be a good starting point for that?
I am happy about any hints that could help me.
Thanks in advance.
lvds3(6) lvds_3_in -- Buffer input );
-- lvds_tick is a clock at 7x pixel-clock (240 MHz)
-- lvds_clk is the clock for the lvds bus, same as pixel clock, but not symmetric
-- like this for one pixel period: --___-- process (lvds_tick,screen_reset) begin if screen_reset='1' then lvds_div