Performing Readback from Impact

I am trying to perform a readback (for the first time) from ISE (impact) on my Virtex II device. For some reason that feature is not enabled (even after I enabled readback feature while programming it.)

I tried finding docs which discuss this, but failed. I did find some resources on how to readback (but not from ISE). I never got a reply from Xilinx Customer service when I filed a webcase!

It would be great if someone can help me.

Thanks.

Reply to
Praveen
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Praveen,

Readback of FPGAs us> I am trying to perform a readback (for the first time) from ISE

Reply to
Neil Glenn Jacobson

Thanks Glenn. Why list that option when we can't use it? ;). I read in the Impact help file that it can be used when using desktop configuration mode. But, I read elsewhere (in Xilinx help file) that suggested it can be used in SMAP and JTAG config modes. Doesn't make any sense.

Reply to
Praveen

Praveen,

The readback operation is supported in iMPACT only for PROMs and CPLDs in Boundary-Scan and Desktop modes. Since iMPACT is a generic Xilinx device configuration tool it indicates the complete set of operations available for ALL devices but disables the ones that are not supported for the selected device.

This is not unusual. For instance, in "Word" you may not be able to Cut or Paste a protected document yet the operation is visible but disabled.

Praveen wrote:

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Reply to
Neil Glenn Jacobson

Hi Neil,

I think what you say is not entirely correct - impact doesnt do FPGA readback, not because it can not support it because Xilinx decided not to include this feature (available to the user).

doing verify with FPGA in iMpact actually DOES readback of FPGA into internal buffer, then compares it to the .BIT file using the .MSK file and then trashes the internal readback. So the FPGA readback is internally used by impact, just the readback can not be saved to a file.

sure the readback would not be the same as the programmed bitstream if the FPGA has been started, eg you would only get the proper .bit being read if the readback is done after JTAG configuration, but before jstart instruction, which I agree would be very rare case indeed. So I kind of understand why the FPGA readback is 'left out' from impact, but it doesnt mean its not possible. the usefullness of the readback is sure a question, there are only a few cases where it could be useful.

Antti

"Neil Glenn Jacobson" schrieb im Newsbeitrag news:d569t5$ snipped-for-privacy@cliff.xsj.xilinx.com...

Reply to
Antti Lukats

Antti,

I didn't say it was impossible. I said it wasn't supported :-)

Antti Lukats wrote:

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Reply to
Neil Glenn Jacobson

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