Hi Folks,
I'm using ECS (yes, I know...). Now, ECS forces one to insert a buffer whenever one wants to rename a bus. I have done so. I was stunned to see that buffer appear in the routed design - as a LUT with D=A1! I'm sure I can get rid of it using the proper XST or PAR options, but I don't know which. Can anybody help?
Thanks a lot Gunter
Hi,
I think the way ECS works is that it writes out a netlist of your schematic in an HDL using instantiated primitives from the UNISIM library. Then, the design is actually synthesized by XST before it heads into MAP and PAR.
By default, XST does not "optimize" instantiated primitives. You can override this option, I think it is called "optimize_primitives" and you'd set it to "yes". Consult the online help system to find the specific name of the option. If you have trouble finding it, file a case with the Xilinx customer support team and they will help you find it.
Eric
Eric,
thanks very much for your answer. However, the problem went away when I upgraded from 6.3 to 7.1. Now the fake buffers are gone without any further action.
Cheers Gunter
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