Latest threads in Field-Programmable Gate Arrays

Q.Timing Simulation using ModelSim for a Xilinx Spartan 2E

Hi... I wonder how to do timing simulation using ModelSim for Xilinx FPGA. I have finished functional simulation for my...

0 21yrs

kim.donghun

0 21yrs kim.donghun

ISE 7.1 small advice about project files (.ISE extension)

Hi just a little thing: starting from 7.1 ISE abondoned the use of plain text project files, the new project files with...

3 21yrs

antti

3 21yrs antti

2:1 mux in one LUT

hi all, can anyone explain me how only one 2:1 mux is implemented in a 4-i/p look up table? Is it just the implementati...

1 21yrs

Puneetsingh81

1 21yrs Puneetsingh81

Async FIFO coregen wizard

I have tried to instantiate the Asynchronous FIFO core (v6) from Coregen, and it's been giving me trouble. First, I can...

1 21yrs

send_no_spam_to_jimgeorge

1 21yrs send_no_spam_to_jimgeorge

V2pro configuration problem - PROM SIZE

Dear One error occurred when I configure V2pro-30 in Project Navigator 6.3. "Specified PROM file untitled.mcs is too la...

0 21yrs

JEmoderatz

0 21yrs JEmoderatz

What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?

Group, I am going to buy some EPM1270T144C5 from digikey.com but they listed both EPM1270T144C5 and EPM1270T144C5N. Wha...

2 21yrs

vax9000

2 21yrs vax9000

State Machines.. and their efficiency.

Hi all, I'm a low-level kind of programmer (and wannabe hardware designer). When I write a piece of code, be it assembl...

3 21yrs

nospam

3 21yrs nospam

ARC A4

Hello... I know that ARC A4 RISC core is mainly intended to go into ASIC... but is there any development platform using...

1 21yrs

me

1 21yrs me

Virtex 4 configuration frames

Hi, We have the following questions related to Virtex 4 configuration frames: a). What is the shape and size of a frame...

3 21yrs

lovesinghal

3 21yrs lovesinghal

Ethernet / digital logic questions

Ok, I'm not designing an Ethernet MAC but I see that people now make FPGA cores for this. I had a few "general" questio...

7 21yrs

localhost

7 21yrs localhost

lpm_counter bug?

Hi, I'm using Quartus 4.1 Web Edition to program a MAX7000S CPLD. I'm using an lpm_counter as a programmable divider wi...

4 21yrs

andrew

4 21yrs andrew

generate systemACE file

h when I generate systemACE file in EDK I am getting the followin error. Anyone can give me some tip how I can get rid...

1 21yrs

kurapati77

1 21yrs kurapati77

powerpc startup

I have made a powerpc system with a user peripheral connected to the plb bus. The user peripheral has an address range...

6 21yrs

someone

6 21yrs someone

Single-endec clocks

How should I connect a single-ended clock source the PLL inputs of a Cyclone? In the manual there are some examples of...

6 21yrs

wyderskiREMOVE

6 21yrs wyderskiREMOVE

Lattice ROM file tool....

Hello.. Is there any tool that generates the .mem ROM files from a binary or intel hex file compatible with Lattice Modu...

1 21yrs

me

1 21yrs me

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