Hi all,
I'm a low-level kind of programmer (and wannabe hardware designer). When I write a piece of code, be it assembly, C or Verilog, I need to have a precise idea of how it will end up. I've began to explore the wonderful world of FPGAs and of the Verilog hardware description language, and while I do understand that combinational logic can be reduced to its minimum terms, and I also understand latches and other sequential logic, I have big problems in figuring how a state machine ends up ("schematically speaking").
Although I've hunted for, and found, some schematics of state machines, I still haven't found a clear explanation and description of them that makes me sleep at night. ;)
My aim is, other than understanding state machines at a intuitive level, to write them in the most efficient way.
When I'm writing combinational code, I know when it will end up in too many logic gates.. same for sequential, but for state machines the "black box" is actually into my mind.
Many Thanks in advance for any attempts to illuminate me.
Greets, Mike