hi all, can anyone explain me how only one 2:1 mux is implemented in a 4-i/p look up table? Is it just the implementation of function O = A(/S) + B.S If this is the case then this implementation uses 3 i/p and only 8*1 locations. I don't know what i am guessing is correct. Please help if i am wrong.
A LUT is usually simply a SRAM in most FPGAs and the 4 inputs act as an address to give a single bit output. Synthesiser tools and backend tools convert your logic into an address and data mapping for your LUT logic and this gets loaded at configuration. Your inputs don't actually pass the input through the LUT like in an analogue mux but directly cause a relevant output to be generated.
You can use only 3 inputs by either mirroring data with the 4th input having no effect or alternatively tying the spare input to a known value and building a 4 input function. Usually this is all handled by the tools for you and is only of concern if you start instantiating raw LUTs in your VHDL or Verilog.
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