Field-Programmable Gate Arrays

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Altera's fast NIOS update service (o;

So for how long is NIOS2 5.0 out? Just received today my NIOS2 1.1 upgrade... Unbelievable fast they are (o; /jedi
3 comments posted 21yrs
posted by me
3 comments posted 21yrs posted by me

How to add a lib to the core used

Hi I am having problems trying to add a plb slave device. I edited the user_logic.vhd file of my core and invoked the C...
3 comments posted 21yrs
posted by johnsons
3 comments posted 21yrs posted by johnsons

PCI master clock trace

Hi Guys, Is there another standard of PCI for master? i think of this because i have observed that clock trace in the m...
5 comments posted 21yrs
posted by praveenkumar1979
5 comments posted 21yrs posted by praveenkumar1979

FPGA : Coregenerator Adaptive FIR Filter

Hi I have used Coregnerator FIR filter in my desing. Initially i have used fixed coefficients, which is stored in BRAM...
0 comments posted 21yrs
posted by pbijoy
0 comments posted 21yrs posted by pbijoy

USB interface With AMBA AHB

Hi Folks, Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI) using AMBA AHB/APB 2.0 Specification?? Your help...
11 comments posted 21yrs
posted by joe.ricky
11 comments posted 21yrs posted by joe.ricky

Clock Generation : FPGA

Hi I am using Spartan-3 fpga I need to generate 35.328 MHz clock I have an external xtal of 35.328 MHz feeding to FPGA....
19 comments posted 21yrs
posted by pbijoy
19 comments posted 21yrs posted by pbijoy

How to speed up float computing--continued

I am very glad to see so many discussions. Thank you! At present I am using the PowerPC, because its bram is 128K, but...
1 comments posted 21yrs
posted by lnzhao
1 comments posted 21yrs posted by lnzhao

how to use GCC compiler

At president I am doing some projects with EDK 6.3i on Virtex-II Pro under Windows XP OS. I want to use the GCC compile...
2 comments posted 21yrs
posted by zln-bg
2 comments posted 21yrs posted by zln-bg

file differece for two xsvf files

Hi, xsvf file can be generate by IMPACT directly, andalso can be generate by svf2xsvf502 from XVF file. So what is the...
0 comments posted 21yrs
posted by suwon27
0 comments posted 21yrs posted by suwon27

Quick way to synthesize pcores in EDK

I am developing a Xlinx Virtex 4 FPGA system and require to change a pcore frequently during the development phase. Whe...
2 comments posted 21yrs
posted by kunal.shenoy
2 comments posted 21yrs posted by kunal.shenoy

C-1 how to reflash..

Hi, I have this ...%#$%#$% commodore=one. Recently it (auto)started an "emergency" flash procecure.. It halted (CRC err...
1 comments posted 21yrs
posted by csynt
1 comments posted 21yrs posted by csynt

mc8051 v1.4 free ip core from Oregano Systems

Hi I've downloaded the .zip file but it seems empty or corrupted I sent an e-mail ( snipped-for-privacy@oregano.at) but...
1 comments posted 21yrs
posted by mikomatik
1 comments posted 21yrs posted by mikomatik

Chipscope and LVDS clock (IBUFGDS)

Hello, i am working with chipscope pro 7.1 with following code: entity BoardTest is Port( led_o : out std_logic_vector(...
0 comments posted 21yrs
posted by Nightstorm
0 comments posted 21yrs posted by Nightstorm