I designed two related cards (not a PCI plug in unit) that had 2 PCIX
133/64 busses, amongst a lot of other things.
My implementation (and it worked) as to assume a 'zero length' motherboard for one of the devices, and set the routing rules appropriately. That part was close up against the bridge. The other part was a significant distance away, so I kept the differential rules between groups and set the routing rules based on maximum track lengths (8 inches for PCIX 133, according to the device manufacturer) and that worked fine as well. I will say it took me as long to set up the rules as it did to draw the schematic :)
The tolerances are somewhat looser than Falk notes. The clock track, for example, if memory serves, was 2.5 inch +/- 0.1 inch on the expansion (plugin) board.
As I noted though, the exact specs are available, and that is what should be used if you want to make a PCI implementation that will work properly.