PCI master clock trace

I believe you will find the 2.5 inches is the clock trace length allowed on an expansion card not main bus segment.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

If you are designing a PCI system, I suggest you get a book on the PCI standard, or get the standard itself from the PCI SIG.

The clocks which go from the host board to the PCI slots are supposed to be matched in length and under some maximum, IIRC. They can actually be pretty long (12" or more) and still work at 33 MHz, but they are supposed to be matched in length.

--Mac

The PCI spec addresses all your questions.

There are two sections on lengths :

Motherboard, where the maximum length of the tracks is defined in terms of time (to make sure the bus remains reflective within specific limits) and

Expansion card, where the lengths of the tracks are specifically spelled out. Note that the high order 32 bits (for 64 bit implementations) have different length requirements, and for 64 bit implementations, you must alsso be careful about the relative length of #REQ64 and #RST (#REQ64 must still be a valid low when #RST is rising through a valid high)

You can get the PCI spec from

The lengths in each section vary depending on just which implementation you are attempting

# bits Speed (MHz)

32 33 64 33 32 66 64 66 PCIX below - in the PCIX supplement 32 100 64 100 32 133 64 133

Cheers

PeteS

"Mac" schrieb im Newsbeitrag news: snipped-for-privacy@bar.net...

AFAIR the trace length on the PCI card (NOT the motherboard/backplane) is supposed to be 1 inch +/- 0.005. Including the tolerances of the backplane, skew is assued to be less than

2ns.

Regards Falk

I designed two related cards (not a PCI plug in unit) that had 2 PCIX

133/64 busses, amongst a lot of other things.

My implementation (and it worked) as to assume a 'zero length' motherboard for one of the devices, and set the routing rules appropriately. That part was close up against the bridge. The other part was a significant distance away, so I kept the differential rules between groups and set the routing rules based on maximum track lengths (8 inches for PCIX 133, according to the device manufacturer) and that worked fine as well. I will say it took me as long to set up the rules as it did to draw the schematic :)

The tolerances are somewhat looser than Falk notes. The clock track, for example, if memory serves, was 2.5 inch +/- 0.1 inch on the expansion (plugin) board.

As I noted though, the exact specs are available, and that is what should be used if you want to make a PCI implementation that will work properly.

Cheers

PeteS