I have an external xtal of 35.328 MHz feeding to FPGA.
From this clock i need to generate 35.328 MHz square wave with fine resolution.
We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution.
I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.
Is there any-other way out ?
( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices.
So i thought of using FPGA for this purpose as an alternative solution. )
taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.
devices.
How would an FPGA be able to achieve a clock that was difficlt to achieve otherwise ? So when a 300MHz DDS is too noisy, rebuilding the DDS with an FPGA is not going to help. What is also not going to help is a PLL with a Phase comparator running at 1Hz. The other possible way would be to single side band modulate your carrier. The probelm there ist the suppression of the other sideband and the suppression of the carrier. In the 35MHz range, a suppression of
40dB should be doable. The existing 35MHz clock would be the LO, of which you'd need another channel 90 degrees shifted. Then you's need the difference frequency, in 1Hz steps, possibly from a DDS, and a pair of mixers. This difference frequency is the IF channel, also required in quadrature, eg 90 degrees shifted.
I'd stick with a DSS and filter the signal. An AD9854 or such.
Hi Rene We are presently using AD9854 but it is too costly for a USB ADSL2+ modem
So i was searching for alternatives. Thats how i reached DDS on FPGA which generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy.
If you start off with a much higher frequency clock, the MSbit from a DDS that produces a phase output (no need to generate a sine if all you're using is the MSbit) won't be as noisy. In the time domain, the DDS jitter will be up to 1 master clock period, peak-to-peak. The clock can be cleaned up with an external 0 delay buffer as long as all the generated spurs are high in frequency, reducing your jitter to a 25 ps class device. The 0 delay buffer isn't $1. A DDS run by a multiple of
35.328 MHz generating 35.328001 MHz will produce an unfilterable 1 Hz spur. The trick is to find something where the tuning range is all high frequency jitter content.
There are plenty of techniques to get extreme precision but they aren't cheap. Consider that the noise of a cheap crystal oscillator will probably wander around the 1 Hz resolution by several Hz depending on temperature, mood, microphonics, and other environmental effects.
Your specs may need to be rec> Hi I am using Spartan-3 fpga
wave out put frequency by 1 Hz resolution.
taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept.
generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy.
Ok, another lower cost alternative could be running two PLLs. There are these ADF4001 for 8$ @100, they operate between 10 and 200MHz. So by taking one as reference for a second... One would have to play with the numbers. Or two of them plus a CPLD. I remeber an article recently that they were achieving rather low difference frequencies. Yep, the article was about how to generate a second frequency very close to the original for sampling purposes. But without long integeration times in the PLLs. I'll look it up.
"John_H" schrieb im Newsbeitrag news:tPDne.35062$GN3.17984@trnddc04...
resolution.
square wave out put frequency by 1 Hz resolution.
Hmm, how about using a cheap VCO based PLL (ala 4046) and a DDS (inside the FPGA) generating lets say 3.5328 MHz. Multiply the 35.328 by four. Run the DDS at this frequency, a 32 bit accu will give a resolution of 0,03 Hz. Use the analog PLL to multiply by ten. This way your frequency resolution is degraded to 0,3 Hz, but this sounds enough for your application. If the loop filter is designed properly the broadband/high frequency jitter is filtered out.
Average frequency resolution is trivial with DDS. I recently built a box that generates 1 Hz to 640 MHz in 1 Hz increments ( and 1 mHz would have meant just another ten stages in the accumulator.) The issue is jitter and stability or "wander". The DDS gives you a whole clock period of systematic and deterministic jitter. So that's a couple of nanoseconds plus the original clock jitter plus DCM jitter. Then you can play all sorts of tricks to reduce the jitter, but don't expect to get below 50 ps of cycle-to-cycle jitter for any adjustable frequency. (Fixed frequency generators with high-Q resonators are a different thing) Agilent can barely get below 40 ps, and they have 60+ years of experience, and charge thousands of dollars...
Then figure out the instantaneous frequency stability:
50 ps @ 100 MHz = 50 parts > "John_H" schrieb im Newsbeitrag
At 35 MHz, the period is around 30 ns. If you change the frequency by 1 Hz, you change the period by 30 ns /
35 million. That is less than one femtosecond. (Less than a thousandth of a picosecond) Light travels 0.3 micron (about half its own wave length) in 1 femtosecond. Just to put things in perspective... Peter Alfke
At 35 MHz, the period is around 30 ns. If you change the frequency by 1 Hz, you change the period by 30 ns /
35 million. That is less than one femtosecond. (Less than a thousandth of a picosecond) Light travels 0.3 micron (about half its own wave length) in 1 femtosecond. Just to put things in perspective... Peter Alfke
I gleam that the idea could be to use a PLL to remove the ugly stuff from a DDS. In my experience, once you have the ugly stuff (noise, glitches, spikes) on your board, it is very hard to get rid of it.
The ugly stuff is hard to remove if it's low frequency ugly stuff. If the jitter frequencies are above the PLL loop frequency, the ugly stuff will go away. The problem is in trying to extract the fundamental frequency +/- a few Hertz from an oscillator with the same frequency. In this situation there *will* be ugly stuff at a few Hertz that can't be filtered by the PLL.
Using a completely unrelated (higher frequency) clock could produce a DDS clock at the desired fundamental frequency +/- a few Hertz with almost all the ugly stuff high in frequency if the unrelated clock is chosen well. A
100 MHz clock will have jitter frequencies at 32kHz and higher which would be cleaned up rather well by many zero delay buffers. The Hertz-offset ugly stuff would be about 3 ps peak-to-peak in this arangement.
If bijoy really needs that 35.328 MHz as both input and (roughly) output frequencies, the DAC DDS approach is probably the cheapest in the end.
"Rene Tschaggelar" schrieb im Newsbeitrag news:42a014b0$0$1161$ snipped-for-privacy@news.sunrise.ch...
Haaa, not sooo fast, my friends ;-)
First, the DDS output will have NO glitches and spikes. So 2 out of 3 are out. Noise is another story. Yeah, digital and analog dont mix well, but ist not impossible.
My idea is. Quadruple the 35.whatever MHz clock using a DCM. Use this clock to drive a simple DDS. No need for a sin rom, just use the MSB as your clock. Generate a clock that is 1/10 of of you desired (fine tuned)
35.whatever clock. With the fixed 35.whatever quadrupled, this gives you a systematic jitter of 1/40 period. Hmm, not too bad. Now use a (cheap) analog PLL with a (cheap) VCO to multiply the 1/10 DDS output by ten. I gues the good ole 4046 isnt fast enough for that, I remeber 30 MHz max. for the VCO. Use a loop filter with a low corner frequency. Somthing in the range of
1/10..1/1000 of the input frequency (which translates in 1/100 ... 1/10,000 of the output frequency) the better the VCO the lower you can go. Imagine, the VCO has to run stable for 100..10,000 cycles before the loop filter will respond to phase drifts.
Another approach would be to use the DDS (running at x4 clock) to directly generate the tunable 35.whatever clock. By using just the MSB again, we end up with a clock with 1/4 period of systematic jitter. Uhhhh. But things can get cleand up. Use a plain Xtal for 35.whatever frequency to build a Xtal filter. This should get rid of all the bad jitter. This way you need just a Xtal, which is less expensive than a full DDS IC (i guess). But after all, why do you need a 1Hz tuning in the xDSL modem? Arn't they supposed to tolerate something like +/- 50 ppm, which is a standard precicion of almost every Xtal?
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@g47g2000cwa.googlegroups.com...
Thats right but not quite the point. If two clocks @ 35MHz are off just by
1Hz (wich is just 0.02 ppm) , it takes just 1 second to reach a phase offset of 1 clock cycle. Can be nasty if two devices talk to each other . . . That why the lord invented PLLs ;-)
The trouble is the Hz-level modulation looks like a saw wave. When the saw hits the vertical cliff, the phase slews as fast as the PLL loop filter allows producing a phase hit. I may have oversimplified the situation by suggesting the spurs are close-in; they're also in harmonics much further up because of the saw function in the phase error.
DDS
all
A
would
But it is rocket science if the input and output frequencies are offset by a few Hertz.
This thread is going around in circles. We know the average frequency is no problem. We also know that jitter is unavoidable, and tends to camouflage the resolution. We do not know why the whole effort is necessary...
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