Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc

Hi Peter,

Have book, will attend.

Even though I'm in the opposite camp, I will definitely join the seminar on Wednesday. I've been to Dr Johnson's lectures before, and I've even found his material appliccable to designs running as low as 32MHz.

Dr Johnson has a very entertaining way of presenting, so the only thing I can do is to second Peter, and thank Xilinx for the opportunity to get an update on my design skills.

Best regards,

Ben

Howard's good but I prefer Rod Strange of Fast Edges Inc for SI ...

...

Peter,

do you know if there will be videos or CD/DVD available for those who can not attend in person ?

Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

TechOnLine provides web-based seminars over the internet. You have two choices:

1. You can participate in real time anywhere in the world, where you also can type in questions to the spaker, who will answer (most of) these questions in the final minutes of the webcast. And some of thee questions have, in the past, been very interesting, and the answers were very informative.
2. You can later listen to these TechOnLine seminars from their archives, at any time you pick. I will describe the procedure tomorrow, when I am back at work.
3. Xilinx is also creating CDs withthe content of these seminars. I will describe that, too.

Peter Alfke, from home.

Ben, Indeed, if you'd read the book ;-) , you'd know it's the rise time and length of the path that matters, not the toggle rate. Cheers, Syms.

Just a reminder, the seminar starts in a few hours. Still time to sign up, learn, and enjoy.

To join us on Tuesday, June 7 at 11 am Pacific Time, 2 pm East Coast time, 1900 in England, and 2000 in Central Europe (sorry, very early in

Asia), register by clicking on

/s/xilinx_jun0705

To join us for the same seminar, one day later and four hours earlier, on Wednesday, June 8 at 7 am Pacific Time, 10 am East Coast time, 1500 in England, and 1600 in Central Europe (sorry, even earlier in Asia), register by clicking on

/s/xilinx_jun0805

Peter Alfke, Xilinx PS. I will soon publish the best way to access the archived seminars.

The seminar was a nice follow-up to the previous one and I thought was well done. I'd like to see a future seminar dealing in more detail with board layout issues that affect signal integrity.

John Providenza

John, Indeed, layout is important. Like put the ground plane as close as possible to the BGA rather than on the otherside of the board to make the Altera parts look unusable. Don't get me wrong, the Xilinx BGA pin layout is superior to the Altera one in terms of SI. However, by using a more realistic stackup, I would suggest the problems are not as pronounced as in today's demo. Also, in the original demo,

, I would question whether the PCB was laid out optimally, or in such a way as to accentuate the problem. Long and adjacent traces far from a ground plane would do this. There's no picture of the stackup or layout in the demo document. From the first demo, the conclusion is :-

The Altera package suffers from two issues:

1.. . Excessively fast signal rise/fall time

2.. . Over-concentration of power/ground balls in core region I'd argue that 1) isn't a problem; fast rise time is good, as long as you know what you're doing. (BTW Xilinx can't compete on risetime because of their 12.5pF pin capacitance.) Now, 2) could be a SI problem, for which the Xilinx package is a solution, but I question whether the data presented are a realistic 'real world' set up. If they are, no-one would be able to drive DDR ram from an Altera part. On the other hand, 2) could be better in terms of signal routing, the traces from the centre of the Altera package don't have to negotiate a lot of power and ground vias as they fan out from the device. In conclusion, I think the Xilinx BGA layout is a good thing. Well done. But, I don't believe the Altera parts have to be as bad as they appear in these demos. And, for differential signals, for which the Altera parts are much better (see above comment about pin capacitance), the BGA layout makes bugger all difference. Cheers, Syms.

p.s. Thanks to Xilinx for these seminars; it shows the subject is being taken seriously.

NOR any detail of the DIE bonding. The total path is what matters.

Are these Xilinx devices flip-chip / direct bonded ?

If so, they should clarify which other xilinx devices are not....

For dI/dT, yes, but slower rise times make poorer eye diagrams...

Most logic interfaces do not try and clock at the same time as the address bus changes, so cross talk becomes mission-serious only onto the write line - and if you are silly enough to choose a WRN strobe, right on the most noisy pin, then you rather deserve to get bitten....

That said, there are other more analog situations where low system noise is a very good thing, and EMC tests would have been interesting.

Probably not in the real world.... The pdf says min 7" traces, and 500 aggressors - and I've never seen a real design come close to either number...

Still, it is an educational test, and good to see simulations and physical correlations.

Comment: The inductive nature of the cross talk, suggests some controlled capacitive crosstalk could actually help counteract/null this

Has anyone actually tried that ?

-jg

Jim, we described Virtex-4, which is 100% flip-chip. This was not a history lesson on the older families, nor on TQ144 packages :-( Peter Alfke

This was a good, useful presentation, particularly the discussion on the utility of "soft grounds."

But it did make me wonder this: with all of the concern about crosstalk, how many designers take the time to separate groups of mutually asynchronous signals when assigning the FPGA pinout? Most of us don't have the luxury of running everything at the same clock speed, and yet I've seen little or no mention of how beneficial it is to separate signals that run at different speeds. Maybe this idea is buried in the docs somewhere, but I've yet to see a single presentation from any vendor that suggests this.

Perhaps this gets little play because it's obvious. But given the number of designs I've seen with I/O signals placed anywhere they'll fit, I think otherwise.

Bob Perlman Cambrian Design Works

Symon, you wrote: "Also, in the original demo,

/virtex4/pdfs/BGA_Crosstalk.pd f , I would question whether the PCB was laid out optimally, or in such a way as to

accentuate the problem. Long and adjacent traces far from a ground plane would do this. There's no picture of the stackup or layout in the demo document. "

We have nothing to hide. I cannot post the files for the 24-layer pc-board (12 MB) and the schematic (another MB) here in the newsgroup, but we have no hesitation to provide them to somebody who needs to know. We did all this without any devious intents. No need for it. We knew that our parts are better (and also consume less power), so we built a board, totally symmetrical, to prove it to ourselves and to others. And it does proves better signal integrity as well as lower power. Some people may not like it. But that's their problem, not ours.

Peter Alfke, Xilinx Applications

Quite understood.

Which other family(s) are also flip-chip ?

-jg

Peter, No need to post the entire thing, all I'd need to know is the stack up, the length and spacing of the traces from the balls to the destination, which layer(s) the traces are on. I agree your pinout is better, let's say 5 times better. The point I'm trying to make is that if the board is laid out so Virtex parts give

50-100mV crosstalk, the Altera parts are down the loo, but if the board is laid out so the Virtex parts give 10-20mV crosstalk, th> "Also, in the original demo,

A single-clock synchronous system can tolerate a surprising amount of ground bounce and crosstalk, since its single clock is safely parked when the outputs change, and the outputs are still stable the moment the clock changes. But give me two (or more) unrelated clocks, and the chip becomes very sensitive to ground bounce and crosstalk, for one clock domain might (i.e. will, sooner or later) change just as the other domain is in its most sensitive state. That can generate uncontrolled clocking hick-ups and other non-repetitive nasty things.

Bob, was this what you had in mind? Of course no news for an experienced guy like you, but might be a valuable warning for naive beginners... Peter Alfke, Xilinx

That's what I had in mind for the problem statement. But once the designer is made aware of the problem, he needs some help in dealing with it. That's where a list of recommendations would come in handy.

Bob Perlman Cambrian Design Works

"Jim Granville" schrieb im Newsbeitrag news:42a61f65$ snipped-for-privacy@clear.net.nz...

Carefull. This only "works" in a small band of resonance. Any wideband signal (NRZ data etc.) won't work with this. Iam not sure if this will work with DC balanced stuff like 8B10 either, since the bandwidth ist still 2-3 decades.

Regards Falk

"Jim Granville" schrieb im Newsbeitrag news:42a61f65$ snipped-for-privacy@clear.net.nz...

Yes, but you dont really want the fastest edges known to man in ALL designs. Would you build a kitchen timer using ECL? Would youl like the FPGAs spitting out 5ps (yes PICOseconds) edges, no matter whats your clock speed? I would put it the other way around. If the Xilinx edges are slower, but STILL look good in the target application (which includes stuff like 800 Mbit/s SPI4.2, 400 Mbit/s DDR-RAM etc.) why asking for more speed which is likely to cause trouble? I think there is a reason why CPLD/FPGA outputs have adjustable drive/slew parameters. And this was also long before the newest Gbit stuff form A and X was on the market.

Regards Falk

designs.

Frankly, yes. Because FPGAs are general purpose devices, your kitchen timer is my DDR RAM controller or ultra fast sampling circuit. The faster the edges, the greater the range of applications for a given FPGA. If this means kitchen timer designers have to learn about SI, well that's the price I'm willing for them to pay! ;-)

But, again, Altera's parts have half(ish) the rise time, which means they can cope with more applications as RAMs go faster. My point is that fast edges don't preclude any applications; crap designers do. The point Dr. Johnson was trying to spin, I mean make, is, I think, that fast edges in combination with a bad package can be unusable. True, of course. That's why you can't get new FPGAs in PLCC packages. What I dispute is whether Altera's packages are that bad at today's rise times. That said, Xilinx's package is superior in terms of ground bounce. What we need is Stratix silicon in a Xilinx package!

Cheers, Syms.