Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

MediaBench

Has anyone taken a C benchmark suite, like MediaBench, partitioned it by hand into C and Verilog or VHDL (or some moral...
0 comments posted 21yrs
posted by benjaminy
0 comments posted 21yrs posted by benjaminy

isplsi1016

Handbuch der PLDs und FPGAs
20 comments posted 21yrs
posted by learnfpga
20 comments posted 21yrs posted by learnfpga

Boot problem Stratix Kit EP1S25

Hi, I've got a big problem with a Altera Stratix Kit EP1S25. We have integrated it in our application... We have direct...
3 comments posted 21yrs
posted by patrick.melet
3 comments posted 21yrs posted by patrick.melet

XP for NIOS2

Hello, why is there neither Windows XP Embedded nor Windows CE port for the Nios2 processor? Does Altera plan to create...
14 comments posted 21yrs
posted by wyderskiREMOVE
14 comments posted 21yrs posted by wyderskiREMOVE

ISE under Linux: 32 vs 64 bits

Hello all, Currently we use Windows and 32 bit Linux versions of ISE. We are looking for a way how to increase speed of...
2 comments posted 21yrs
posted by jenda76
2 comments posted 21yrs posted by jenda76

Protecting IP in China

Sorry to bring up this old topic again. Does anybody know how easy/hard it is to enforce IP Laws in Taiwan ? Technicall...
3 comments posted 21yrs
posted by russelmann
3 comments posted 21yrs posted by russelmann

keypad scanner

Hi all, I am implementing a 6x6 matrix keypad scanner in CPLD. My requirment is i should detect multiple key presses al...
14 comments posted 21yrs
posted by praveen.kantharajapura
14 comments posted 21yrs posted by praveen.kantharajapura

how can i extend my code space to extern memory?

I want to extend my program to extern RAM in EDK, But i can't find any document about assemble program of MICROBLAZE or...
2 comments posted 21yrs
posted by mlpei279
2 comments posted 21yrs posted by mlpei279

Spartan 3 ata interface

I'm working on a simple ide interface to a spartan 3 fpga. I've gone over the ata specs and online projects and I keep...
6 comments posted 21yrs
posted by Terradestroyer
6 comments posted 21yrs posted by Terradestroyer

How do I instantiate GT11CLK_MGT?

The Virtex-4 lib manual suggests that the Architecture Wizard should be used, however I can't see how... The Virtex-4 Ro...
1 comments posted 21yrs
posted by mbmsv
1 comments posted 21yrs posted by mbmsv

UARTlite problem..!!!

Hi, I am receiving some data from the uart.I take it and keep it in memory using a pointer.I use the following conditio...
1 comments posted 21yrs
posted by fpga00
1 comments posted 21yrs posted by fpga00

Basics FPGA

Hi Everyone, I am an electrical engineer but I have never had a chance to learn about FPGAs. I think now is a time to m...
15 comments posted 21yrs
posted by shantanu.pathak
15 comments posted 21yrs posted by shantanu.pathak

ppc405 cache using bram

Hi I've got a question concerning the use of BRAM connected to the Dat Cache Unit. Does the processor still use the int...
2 comments posted 21yrs
posted by PeterSchlez
2 comments posted 21yrs posted by PeterSchlez

some mistakes with EDK7.1i

Hi All, I installed EDK7.1i on my computer and built a project. but there are always mistakes. (1): when i download the...
3 comments posted 21yrs
posted by lnzhao
3 comments posted 21yrs posted by lnzhao

Re: problem with edk 7.1

When having compiler errors always look at the very first error first: > In file included from inbyte.c:2 > > ../../../...
0 comments posted 21yrs
posted by mbmsv
0 comments posted 21yrs posted by mbmsv