Field-Programmable Gate Arrays

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Motion controller design with CPLD

Hi there I would like to design Motion Controller (Single axis) with Xilinx FPGA or CPLD. Please send me if you have de...
5 comments posted 21yrs
posted by engtech1
5 comments posted 21yrs posted by engtech1

DDR desing with FPGA

Hi I hope someone has more experience and can give advice - what I need (for urgent customer design) is simple? design...
8 comments posted 21yrs
posted by antti
8 comments posted 21yrs posted by antti

anyone tried the Actel ProASIC3 Starter Kit?

Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of this unit? From the documentation, the chip claims...
4 comments posted 21yrs
posted by starfire151
4 comments posted 21yrs posted by starfire151

In-system configuration

Hi All, I would like to use an FPGA to reconfigure another FPGA by loading the new configuration into the other FPGA's...
2 comments posted 21yrs
posted by ernielin
2 comments posted 21yrs posted by ernielin

linker script

hi, I am working with linker scripts for the first time.I want to understand the linker script that the tool generates f...
1 comments posted 21yrs
posted by kittyawake
1 comments posted 21yrs posted by kittyawake

Memory management : microblaze system

hello all, I have some questions related to memory management in a microblaze system.I am collecting some data which ge...
1 comments posted 21yrs
posted by fpga00
1 comments posted 21yrs posted by fpga00

Available under the terms of the SignOnce IP License

Hallo, I would buy a ip core. What does it means: "Available under the terms of the SignOnce IP License" ??? Thanks Marc...
6 comments posted 21yrs
posted by marcotoschi_no_spam
6 comments posted 21yrs posted by marcotoschi_no_spam

searching spartan-3

Hi all, I am searching XC3s200 or XC3s100 in TQ144 package. Please let me know if you have any stock, 20-100 pces. Email...
1 comments posted 21yrs
posted by laurent.gauch
1 comments posted 21yrs posted by laurent.gauch

QuickLogic FPGA : In-Circuit Programming

Hi all, I'm getting started with QuickLogic FPGAs, and I was wondering if anyone has experience programming the QuickRA...
1 comments posted 21yrs
posted by vadimv
1 comments posted 21yrs posted by vadimv

Boot problem Stratix Kit EP1S25

Hello, I'm working on a project where we utilize 2 EP1S25 Stratix Evaluation board. We have directly connected +5V, +3....
0 comments posted 21yrs
posted by patrick.melet
0 comments posted 21yrs posted by patrick.melet

Connecting two INOUT ports

Hi all, is it legal to connect two INOUT ports in VHDL? If legal then what precautions we have to take to ensure proper...
1 comments posted 21yrs
posted by Puneetsingh81
1 comments posted 21yrs posted by Puneetsingh81

false path on asyn. fifo

Dear all: I am working on Virtex2 Pro on Xilinx. In the design, I instantiated an asynchronous fifo from coregen. The t...
1 comments posted 21yrs
posted by tyf
1 comments posted 21yrs posted by tyf

why my SDRAM test failed in EDK7.1i?

I have built a new project with two SDRAM(each 32M) in EDK7.1i,and used the original memory test program,i find the fir...
0 comments posted 21yrs
posted by mlpei279
0 comments posted 21yrs posted by mlpei279

Atmel CPLD development tools for verilog

Hi, Currently I have verilog design files ready for a CPLD implementation and am planning to use a Atmel AT15xx series...
0 comments posted 21yrs
posted by sridevi.chandrasekhar
0 comments posted 21yrs posted by sridevi.chandrasekhar