Field-Programmable Gate Arrays

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How to deal with misplaced module in ISE?

I am using iSE6 to test a opencores project. All the files are in good order, however, when the files were added to the...
0 comments posted 21yrs
posted by Krist_Neot
0 comments posted 21yrs posted by Krist_Neot

[Verilog] How to write a barrel shifter?

Hi all, How to write a barrel shifter in Verilog? Any easy approaches will be appreciated! Best regards, Davy
2 comments posted 21yrs
posted by zhushenli
2 comments posted 21yrs posted by zhushenli

Anonymous structs in Microblaze C compiler

I am trying to figure out what version of GCC the mb -gcc is based on. This will tell me if I can use anonymous structur...
2 comments posted 21yrs
posted by jweese
2 comments posted 21yrs posted by jweese

faster Spartan III adder

Hi, I need to add a pair of 8 bit (unsigned) integers to get a 9 bit (unsigned) result at 250 MHz, preferably in an XC3...
20 comments posted 21yrs
posted by ptsmith
20 comments posted 21yrs posted by ptsmith

Nios Stratix

Hi, I'm trying to use a NIOS Kit Eval Board (Stratix10). I would like to do a small application : => incr a counter val...
0 comments posted 21yrs
posted by bhb22l
0 comments posted 21yrs posted by bhb22l

ISE/EDK 6.3 vs 7.1...

I tried both ISE/EDK 7.1 and 6.3 (all with latest service pack, bu tested very quicly), and I'm having some problems wi...
8 comments posted 21yrs
posted by bigboytemp
8 comments posted 21yrs posted by bigboytemp

Lattice and Mentor seminar info pieces...

Hi some info from the Lattice roadshow seminar at Mentor 1) 0.9 and 0.65 !? products are coming... 2) new FPGA products...
4 comments posted 21yrs
posted by antti
4 comments posted 21yrs posted by antti

Measuring DDR SDRAM

Hi, maybe someone has had any experience on the following problem: I am searching for guidelines on measuring data line...
0 comments posted 21yrs
posted by ALuPin
0 comments posted 21yrs posted by ALuPin

VirtexII:DCM:CLKFX phase delay

Can anyone tell me which is the phase delay between input and output(CLKFX) when there is no feedback (Input frequency l...
6 comments posted 21yrs
posted by yscdi62k001
6 comments posted 21yrs posted by yscdi62k001

nios32 -> nios2 assembly porting?

Hello... Is ther any document/app-note/how-to for porting an existing nios32 assembly program to nios2 version? Especia...
1 comments posted 21yrs
posted by me
1 comments posted 21yrs posted by me

Simulation problems virtex II

Hi everyone, I have been trying to get a good behavioral simulation going of a Virtex2 on the ML310 board. I'm trying t...
0 comments posted 21yrs
posted by zoinks
0 comments posted 21yrs posted by zoinks

Virtex2 simulation madness

Hi everyone, I have been trying to get a good behavioral simulation going of a Virtex2 on the ML310 board. I'm trying t...
0 comments posted 21yrs
posted by zoinks
0 comments posted 21yrs posted by zoinks

Fast/low area Sorting hardware.

Hi all , I wanted to implement a fast and low area sorting algorithm in Verilog RTL, does anyone have any suggestions? A...
13 comments posted 21yrs
posted by john.deepu
13 comments posted 21yrs posted by john.deepu

Signed/unsigned divider

Hello, I'm trying to generate a divider core with Xilinx core generator I'm confused about the signed/unsigned option,...
2 comments posted 21yrs
posted by vincesusu
2 comments posted 21yrs posted by vincesusu