Latest threads in Field-Programmable Gate Arrays

Need application note for Motion controller with Xilinx

Hello sir This is Seoul Korea. I'm Mr. Lee. The reason that I'm writing letter is regarding for Application note for Mo...

1 21yrs

engtech1

1 21yrs engtech1

USB2.0 UTMI Free IP Core Implentation

Hello, I search some informations about the Free IP core from opencore.org. I would like to implement it on my FPGA Spa...

0 21yrs

sayskimariano

0 21yrs sayskimariano

Xilinx Spartan 3 DCI Power Consumption

Hello everyone, Does anyone have any good numbers for the power consumption used by the DCI circuitry on the I/O's? The...

1 21yrs

spam1

1 21yrs spam1

Xilinx

What mess files!

4 21yrs

qisun

4 21yrs qisun

what's my problem with downloading?

Hello! I am use Xilinx Platform Studio to download the bitstream of an example into ML401 board. I follow the steps whi...

0 21yrs

qisun

0 21yrs qisun

Good FPGA introduction book ?

Hi, I'm starting to learn FPGA programming (using a Xilinx Spartan II 200K). I will use VHDL and already have bought VH...

11 21yrs

someone92

11 21yrs someone92

BGA Rework/Prototype Placement Anyone?

(This was originally posted on sci.electronics.design and was intended to be cross-posted to these groups but that got...

5 21yrs

spam1

5 21yrs spam1

uart / Nios2

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART,...

3 21yrs

bhb22l

3 21yrs bhb22l

Xilinx MAP problem (>1 External Macro Output Pin on single net)

Hi Everyone, I would be really for any help or advice you can offer me on the following. I have created a simple tri-st...

5 21yrs

i.colwill

5 21yrs i.colwill

question regarding "Add I/O buffers" option - SOS

Hi ppl, I previously asked something similar. The thing is that I am integrating a design of somebody who's been using...

2 21yrs

muravinv

2 21yrs muravinv

LUT, how to?

Hello everybody, I'm a newbye in FPGA so I need some help in a simple problem. I would like to implement a 256 byte LUT...

9 21yrs

giovanniparodi79

9 21yrs giovanniparodi79

Deisgn partitioning issues

Hi comrades, I am into hardware design and eventhough I have designed for many components and modules one question alwa...

4 21yrs

zingafriend

4 21yrs zingafriend

MINI PCI card for testing FPGA MINIPCI core

Hello Guys, I am integrating an MiniPCI core on virtex 2 pro fpga. In order for me to test the core i need an MINI card...

0 21yrs

stud_lang_jap

0 21yrs stud_lang_jap

convert vhdl to edif

hi all, I am trying to find some means of converting a design described as a vhdl code to edif file. I am using xilinx...

2 21yrs

narayan.subramanian

2 21yrs narayan.subramanian

Availability of Spartan3

Does anyone know if there is a specific problem leading to long lead times for the Spartan3. Someone from one of the ma...

19 21yrs

barrinst

19 21yrs barrinst

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays