Field-Programmable Gate Arrays

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USB2.0 UTMI Free IP Core Implentation

Hello, I search some informations about the Free IP core from opencore.org. I would like to implement it on my FPGA Spa...
0 comments posted 21yrs
posted by sayskimariano
0 comments posted 21yrs posted by sayskimariano

Xilinx Spartan 3 DCI Power Consumption

Hello everyone, Does anyone have any good numbers for the power consumption used by the DCI circuitry on the I/O's? The...
1 comments posted 21yrs
posted by spam1
1 comments posted 21yrs posted by spam1

Xilinx

What mess files!
4 comments posted 21yrs
posted by qisun
4 comments posted 21yrs posted by qisun

what's my problem with downloading?

Hello! I am use Xilinx Platform Studio to download the bitstream of an example into ML401 board. I follow the steps whi...
0 comments posted 21yrs
posted by qisun
0 comments posted 21yrs posted by qisun

Good FPGA introduction book ?

Hi, I'm starting to learn FPGA programming (using a Xilinx Spartan II 200K). I will use VHDL and already have bought VH...
11 comments posted 21yrs
posted by someone92
11 comments posted 21yrs posted by someone92

BGA Rework/Prototype Placement Anyone?

(This was originally posted on sci.electronics.design and was intended to be cross-posted to these groups but that got...
5 comments posted 21yrs
posted by spam1
5 comments posted 21yrs posted by spam1

uart / Nios2

Hi, I 'm trying to use UART with NIOS2 (Stratix). I would like to send a message to Hyperterminal. (not with JTAG_UART,...
3 comments posted 21yrs
posted by bhb22l
3 comments posted 21yrs posted by bhb22l

question regarding "Add I/O buffers" option - SOS

Hi ppl, I previously asked something similar. The thing is that I am integrating a design of somebody who's been using...
2 comments posted 21yrs
posted by muravinv
2 comments posted 21yrs posted by muravinv

LUT, how to?

Hello everybody, I'm a newbye in FPGA so I need some help in a simple problem. I would like to implement a 256 byte LUT...
9 comments posted 21yrs
posted by giovanniparodi79
9 comments posted 21yrs posted by giovanniparodi79

Deisgn partitioning issues

Hi comrades, I am into hardware design and eventhough I have designed for many components and modules one question alwa...
4 comments posted 21yrs
posted by zingafriend
4 comments posted 21yrs posted by zingafriend

MINI PCI card for testing FPGA MINIPCI core

Hello Guys, I am integrating an MiniPCI core on virtex 2 pro fpga. In order for me to test the core i need an MINI card...
0 comments posted 21yrs
posted by stud_lang_jap
0 comments posted 21yrs posted by stud_lang_jap

convert vhdl to edif

hi all, I am trying to find some means of converting a design described as a vhdl code to edif file. I am using xilinx...
2 comments posted 21yrs
posted by narayan.subramanian
2 comments posted 21yrs posted by narayan.subramanian

Availability of Spartan3

Does anyone know if there is a specific problem leading to long lead times for the Spartan3. Someone from one of the ma...
19 comments posted 21yrs
posted by barrinst
19 comments posted 21yrs posted by barrinst

Using BUFGMUX component in Spartan-3

Has anyone had any experience directly implementing BUFGMUX components in a Spartan-3 device. I know this sounds like a...
0 comments posted 21yrs
posted by paul.bobko
0 comments posted 21yrs posted by paul.bobko