Xilinx

Too many useless files.

when u become experienced in xilinx, they ain't useless files. every file serves a purpose.

Yes, but it might be nice if most of these files were put into a subdirectory so they don't clutter up the project directory.

Best wishes, --Phil Martel "Frank Chee" wrote in message news:d90gun$d8p$ snipped-for-privacy@mawar.singnet.com.sg...

I agree that Xilinx should do this by default. On the other hand, it is easy to set up your project so that this is done. For example, I have the folder structure: range_fpga - |-range_hdl | |-range_ise | |-...

The range_ise folder contains the range_ise.npl project file, and all the generated files.

When adding hdl files to the project, navigate to the *_hdl directory, and add them. This results in entries in the *.npl file that look like: SOURCE ../range_hdl/range_pkg.vhd SOURCE ../range_hdl/ref_pkg.vhd ...

That keeps everything nicely separated.