Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

NIOS2 exceptions...

Evening... Seen in u-boot source code that before returning from an interrupt the return address is adjusted by "-4"......
1 comments posted 21yrs
posted by me
1 comments posted 21yrs posted by me

Xilinx seminar is free AND low cost!

Seen on the Xilinx web site: "Attend a FREE Low Cost Seminar near you" It's actually free, not low cost. Leon
1 comments posted 21yrs
posted by leon_heller
1 comments posted 21yrs posted by leon_heller

Stratix Kit EP1S25 Boot problem

Hello, We utilizes 3 stratix kit dsp board EP1S25 where we have disconnected the +5V, +3.3V, +1.5V voltage regulator an...
1 comments posted 21yrs
posted by patrick.melet
1 comments posted 21yrs posted by patrick.melet

VHDL Synthesis tutorial

Hi, Can any body help me by giving website address or info about VHDL synthesis coding techniques. Thank u. Hima.
5 comments posted 21yrs
posted by himassk
5 comments posted 21yrs posted by himassk

Memec S3-1500 board + P160 comms 2

Hi, Has anyone tried connecting the P160 Comms2 module to the Memec S3-1500 board? Using Base System Builder with Memc'...
2 comments posted 21yrs
posted by jwilliams
2 comments posted 21yrs posted by jwilliams

Where to buy a Xilinx XCR3384XL tq144 CPLD?

Does anyone know where can I buy a Xilinx XCR3384XL tq144 CPLD? Thanks in advance Best Regards Bruno
2 comments posted 21yrs
posted by bmscc
2 comments posted 21yrs posted by bmscc

errors during MAP

Hello, Could you, please, give any insight on what can cause the following errors (i got many)? I also have the same er...
0 comments posted 21yrs
posted by muravinv
0 comments posted 21yrs posted by muravinv

Problem for xilinx!!!

hi....Please help me for a programmer xilinx XC9536XL (parallel LPT When i starter to program, it stopped on "Error:IMP...
14 comments posted 21yrs
posted by dejavu99
14 comments posted 21yrs posted by dejavu99

Auto pipeline logic??

Hi all, Using HDL to pipelining manually is a hardy task. And I found some tools like Synplify have pipeline tools. But...
12 comments posted 21yrs
posted by zhushenli
12 comments posted 21yrs posted by zhushenli

question - NGC & NGO files & integration

Dear all, I need some help with this one. I am integrating a design of somebody who's been designing using schematic an...
1 comments posted 21yrs
posted by muravinv
1 comments posted 21yrs posted by muravinv

PCI arbiter doubt

Hi all, I have some basic doubts on PCI arbiter. 1)how is the framen controlled -- i guess it is a shared resource on t...
0 comments posted 21yrs
posted by praveen.kantharajapura
0 comments posted 21yrs posted by praveen.kantharajapura

Somewhat OT - falling behind the times ...

As someone who is still working with Spartan II, I was amused to see that my mothers new television has a Spartan 3 ins...
9 comments posted 21yrs
posted by dave.garnett
9 comments posted 21yrs posted by dave.garnett

generating 90, 180 and 270 shifts

Hi, I'm still working on creating a DDR interface for an OCM bus. The problem I now face is the following: I need "shif...
2 comments posted 21yrs
posted by zoinks
2 comments posted 21yrs posted by zoinks

Viewing internal signal in Modelsim (post P&R)

Hi all, I am using ModelSim PE 6.0d. I have done functional simulation for my design (i could view all internal signals...
3 comments posted 21yrs
posted by Puneetsingh81
3 comments posted 21yrs posted by Puneetsingh81