Field-Programmable Gate Arrays

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ip core supply

plz touch me more detail if u need the following ip. brahms snipped-for-privacy@yahoo.it ******************************...
3 comments posted 21yrs
posted by brahms_view
3 comments posted 21yrs posted by brahms_view

PROM Generation question

I wanted to generate a set of .MCS files for a Xilinx XC2V3000 design, the board uses three XC18V04 PROMs in serial mod...
7 comments posted 21yrs
posted by jimgeorge
7 comments posted 21yrs posted by jimgeorge

init ProASIC3 Ram from spi

Hello... Wasn't there once an application note on Actel.com for initialising internal RAM from an SPI memory? rick
2 comments posted 21yrs
posted by me
2 comments posted 21yrs posted by me

from email into FPGA !!

Hi I am very glad to announce that the very first succesful 3rd party reference design has been verified on the smalles...
1 comments posted 21yrs
posted by antti
1 comments posted 21yrs posted by antti

TDI routing in Virtex E FPGA.

Hi all, Please help me with JTAG routing. How can i connect the TDI of the FPGA to a I/O pad. I want this connection in...
1 comments posted 21yrs
posted by vssumesh_asic
1 comments posted 21yrs posted by vssumesh_asic

Cannot find net in ucf, but it's there....

I'm getting the error during building that it cannot find a certain net that is referenced in the .ucf file. But the ne...
5 comments posted 21yrs
posted by zoinks
5 comments posted 21yrs posted by zoinks

XST: setting top-level generics

I guess this is more of a Xilinx question than a VHDL question. Anyways, once again, I find myself wanting to set the v...
3 comments posted 21yrs
posted by Bassman59a
3 comments posted 21yrs posted by Bassman59a

PPC405 Question

Hi, I am working with the PPC405 processor on a Virtex2Pro board and was wondering if it's possible to access the reser...
2 comments posted 21yrs
posted by maleche
2 comments posted 21yrs posted by maleche

Cyclone online store

Evening (o; Besides Altera's own online shop... ...is there a distributor in Europe selling them online as well? thx ric...
0 comments posted 21yrs
posted by me
0 comments posted 21yrs posted by me

edn macro in ISE

I like to use a Xilinx written macro (edn) in my design using ISE 6.3. I seems ISE does not accept edn file. I could no...
1 comments posted 21yrs
posted by yaseenzaidi
1 comments posted 21yrs posted by yaseenzaidi

Clock buffering in VirtexE FPGA

I am new to this group and new to FPGA. I am working with XCV2000E fpga. Tool i am using for synthesiz is Xilinx ISE 6....
16 comments posted 21yrs
posted by vssumesh_asic
16 comments posted 21yrs posted by vssumesh_asic

synthesis problem

Hello I have a strange problem. I am trying to implement a decoder as a plb peripheral. The problem appears when I am t...
3 comments posted 21yrs
posted by johnsons
3 comments posted 21yrs posted by johnsons

Hex files in simulation

Hi, in my simulation I have a dual port Ram (from QuartusII v.5.0) which is initialized to all zeros with a hex file. M...
3 comments posted 21yrs
posted by ALuPin
3 comments posted 21yrs posted by ALuPin

ADPLL for NRZ

Hi, I am trying to find some literature of how to design All Digital PLL which would extract clock from NRZ signal. The...
14 comments posted 21yrs
posted by jovajsha
14 comments posted 21yrs posted by jovajsha