I'm getting the error during building that it cannot find a certain net that is referenced in the .ucf file. But the net does exist. It's an input clock signal that is defined in the VHDL file and the MPD. Is tehre somewhere else I need to define it for the ucf to be able to locate it?
Thanks again. (Sorry for so many questions...)
Jim Tuilman
I'll try that, thanks. Altough I never used floorplanner, or the FPGA editor. I just started this 2 months ago :)
I already found the problem:
apparentlythe ucf files are case sensitive, and I forgot a cap d'oh!
Yep -- That's one reason why it's usually convenient to start out with no constraints and run the tools once. Then back-annotate the pin list into the .ucf. Then you'll have all of the pins and their (assigned-by-the-tools locations. You can then go in with a text editor and change the pin locations, or use the GUI to do it.
-a
Another small hint:
if you are trying to constrain internal nets, make sure you did not select the flatten option. If your design is flattened, the hierarchy and net names will change and will be renamed.
Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,
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