Hi,
in my simulation I have a dual port Ram (from QuartusII v.5.0) which is initialized to all zeros with a hex file.
My problem:
After some write operations into the RAM (32 write positions are provided by a FIFO module) I want to reset my design in my VHDL simulation (Modelsim) because the FIFO is empty. The present state of design does not allow to put back the write positions into my FIFO.
After the FIFO is empty I could reset my design within my testbench. But the contents of the RAM should also be resetted or rather be initialized again with zeros. I could step through my RAM and write at each address zeros into it but that takes too long for simulation. The hex file seems to have a bearing on initialization only at the beginning of the simulation.
Is there some possibility to initialize the RAM during simulation by means of the hex file ?
Any suggestions are appreciated.
Rgds Andr=E9