Latest threads in Field-Programmable Gate Arrays

Small FPGA

Hello, I'd like to find a really small FPGA that I could solder by hand, like in a VQ44 or VQ64 package. Ideally, it sh...

13 21yrs

com.246tNt

13 21yrs com.246tNt

xp3/xp6 in ispLever

Hello Does someone knows when XP3/6 devices can be used in ispLever Base 5.0? Lattice said that samples for them should...

1 21yrs

me

1 21yrs me

Linux 2.6 on the Xilinx ML310 board

I haven't been able to find any useful resources on how to install the new Linux 2.6 kernel on the ML310 board. Does an...

3 21yrs

sgowal

3 21yrs sgowal

Clock buffers on the Viretx E

The xilinx tool is forcing the external clock input to the internal clock buffer. And this buffer can take input from o...

0 21yrs

vssumesh_asic

0 21yrs vssumesh_asic

Soft core for MPEG codec

Hi, I am looking for free MPEG soft-core to be implemented in FPGA.Can anybody give some pointers? Thanx for the help. R...

0 21yrs

sanjaypratapsingh

0 21yrs sanjaypratapsingh

Xilinx Virtex 4 device technology

Does anybody happen to know the if Xilinx Virex 4 and/or the QPRO familiy of devices are fabricated using the fully dep...

10 21yrs

amrahmadain

10 21yrs amrahmadain

APEX 20K PLL

Hi; Can anyone give a instruction on how to implement "altclklock" (PLL) for EP20K200E fpga in details? PLL input clock...

1 21yrs

zhg.liu

1 21yrs zhg.liu

INFO:Par:252 - The Map -timing placement will be discarded

Hello, I get a strange INFO message in ISE 7.1 that i have not got in ISE 6.x -----------------------------------------...

0 21yrs

muravinv

0 21yrs muravinv

WTB FutureElectronics Cyclone NiosII Kit

I am looking for a Future Electronics Cyclone NiosII Development Kit with a 1C12 Cyclone FPGA. It was on sale last month...

0 21yrs

jjcain

0 21yrs jjcain

V4 and NBTI question, again..

Hi Xilinx answer record 21127 and related information, - I am still a little unsure if I did understood it all correctl...

11 21yrs

antti

11 21yrs antti

CPU address to OCM address translation

How exactly does the address translate to an OCM address? I can't really find anything solid on the matter and I looked...

0 21yrs

zoinks

0 21yrs zoinks

proth siever in FPGA?

Hello, I know FPGA's are not suitable for sieving large numbers however one set of numbers (Proth numbers, related to t...

9 21yrs

alex

9 21yrs alex

Control IPIF signals

Hi I have a small Question. How can I control this Bus2IP_BE signal in my C code? Joey

1 21yrs

johnsons

1 21yrs johnsons

Good FPGA for an encryptor

Hello, I would like to build a 1GBit/s data encryptor/decryptor using an FPGA chip, but I have a big problem with an ap...

43 21yrs

wyderskiREMOVE

43 21yrs wyderskiREMOVE

USB 2.0 core with 1.1 tranceiver problem

Hello, I'm trying to imlpement an USB 1.1 Device on FPGA (Virtex2). Therefore I first used the USB 1.1 Core from Rudolf...

7 21yrs

michaeldre

7 21yrs michaeldre

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