Avnet V2P development kit woes

Has anyone used avnet's V2P development kit? if so maybe you could help with some questions i've been struggling with. I am trying to use the device without using the PPC or EDK. I am trying to write data over the PCI bridge (a spartan IIe) to a shared SRAM, or data directly from the bridge through to the V2P if possible.

I've been perusing the schematics and VHDL included with the simple memory project. One thing that I still don't understand is how the V2P gives control of the shared sram bus to the pci controller. I can see the signal TRGT_IRQ is a request from the pci for ownership of the bus, but how does the V2P respond to that request and through which I/O pin (to the bridge)? Also I downloaded the schematic for the sram (CY7C1062AV33) and notice that most of the data/control signals in the sram schematic map to the V2P directly (as far as the labels of the control signals). Some don't. For instance the sram has only 19 address pins whereas the V2P has 24 address pins. Which of these map to the 19 pins on the sram (through the Spartan)? Since there is one memory bus that is connected to SDRAM, Spartan2e, V2P. What determines which device will be written to/read from. Is this simply handled through a memory address offset? Also there are three pins (CE1,2,3) on the sram that seem to map to one signal (SRAM_CS_L). Is this correct? I cant really tell how they are being mapped since the bridge design docs dont really explain it.

thanks for your help,

Geoffrey Wall
Masters Student in Electrical/Computer Engineering
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geoffrey wall
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My guess is that you would have an address decoder - this is the standard way - for instance, given 4 equal size memory spaces, you can drive a chip select off the top two bits, ie

00xxxxxxxxxxxxxxxxxxxxxxxxxxxxx = Device 1 01xxxxxxxxxxxxxxxxxxxxxxxxxxxxx = Device 2 10xxxxxxxxxxxxxxxxxxxxxxxxxxxxx = Device 3 11xxxxxxxxxxxxxxxxxxxxxxxxxxxxx = Device 4

Likely - often these devices have multiple chip enables, some active-high and some active-low, so that you can bank a few of them up with a few bits of copper, rather than having to have an extra address decoder. You'd have to check the datasheet for the ram, and see if the SRAM_CS_L signal is driven out as-is to the RAM (check if it matches).

You might want to try simulating the design, to see how it works - build a board level testbench and a simple PCI stimulator, and see what it does. This might be an easy way of better understanding the design. Often the memory manufacturers have models of their chips (in verilog, vhdl or other format), which may help. I suspect you may have to find some further documentation as well. Are there other sample designs? You may be able to compare them to glean more information.


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Jeremy Stringer

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