Max Sample Rate for Signal Tap in Altera Quartus?

Hi Joe,

Since SignalTap is just like any other circuit in your FPGA, the answer would be the same as for, "How fast can a circuit run in my device?"

It entirely depends on what else is part of the FPGA design, on what embedded memory SignalTap uses for buffers, how many signals you are watching, the device itself, and so on. SignalTap can slow down, or be slowed down by, the circuit it is inspecting.

Practically, I haven't had much problem with SignalTap not being fast enough. Even in the cases where timing isn't met, I slow down the design sufficiently so it's not a problem, since SignalTap is only used in the debug phase for me.

HTH

-- Pete

snipped-for-privacy@hotmail.com wrote:

Hello,

My FPGA is running at 80Mhz and I've heard the max sample rate is

joe

Peter Sommerfeld wrote:

schrieb im Newsbeitrag news: snipped-for-privacy@g47g2000cwa.googlegroups.com...

If you have a "modern" FPGA, 80MHz should be no problem for SignalTap...

Thomas

The maximum sample rate of SignalTap depends on, in order of importance:

1. device (faster device families run SignalTap faster)
2. speed grade
3. SignalTap options. The strongest effect is from the number of acquisition channels being used in the trigger condition -- larger numbers slow the maximum acquisition rate down some.

For the fastest Stratix speed grade (-5), the maximum acquisition rate varies from about 200 MHz to about 270 MHz, depending on the SignalTap options you select. For the Stratix -7 speed grade, maximum acquisition rate varies from about 160 MHz to about 220 MHz, again depending on your SignalTap options.

So 80 MHz definitely shouldn't be a problem.

Since Stratix II is 50% faster than Stratix on average, a Stratix II-3 should run SignalTap approximately 50% faster than the Stratix-5 number above, but I don't have hard results on that in front of me.

Regards,

Vaughn Altera [v b e t z (at) altera.com]