Ethernet reference design for ML310?

Is there a simple tutorial or reference design available that implements the ethernet IP from Xilinx? I have stepped through the "Creating a Linux BSP and System Image for the Base Design" tutorial provided by Xilinx and would now like to incorporate ethernet support as a step closer to building something closer to the MontaVista Linux reference system provided with the board. Any advice or pointers?

Thanks in advance, Joey

Reply to
Joseph
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After looking more closely at the block diagram of the ML310:

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It looks like what I really want is to add a pci bridge on the opb bus. Given a functional bridge, it should recognize NIC on the board as a PCI device, right? Can anyone verify that I am on the right track?

Thanks

Reply to
Joseph

Well, the diagram shows that all of the interesting IO is on the pci bus. Wouldn't make much of a Linux machine without that bus.

If that's already in the BSP, then yes else you write PPC405 code.

Can anyone verify that I am on the right track?

You can. Try it and see.

-- Mike Treseler

Reply to
Mike Treseler

Thanks for the response Mike. I have tried two different approaches and in each I have come up with errors I can't get around.

First I tried including the PCI bridge core to the base linux design that Xilinx provides, I realized that it would be better to see how a PCI bridge is included by the Base System Builder so I made a dummy system with PCI capability. Found out I also need a pci_arbiter and another DCM module. The number of connections and ports were a bit overwhelming to do by hand so I abandoned trying to 'upgrade' the base system provided.

I instead tried to build a system from scratch that had all the parts the provided reference system had but with a PCI bridge and arbiter. Went through and made minor adjusments to some parameters in the software platform settings and the address mappings and built my BSP. When I try and generate my bitstream, I get an error in PAR:

ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any Primary / Secondary pair of clocks may enter any region. For further information see the "Global clocks" section in the V-II Hand-Book (Chapter 2: Design Considerations)

This worries me because I didn't make any changes to what the base system builder generated that should affect placement (or so I think). What should I look at to fix this sort of error? I do see that I have more DCM modules than the reference system (4 vs 2) due to the inclusion of PCI. Any advice on where I should look or an explanation of this error (did some searching on it and no reference to this error with 6.3i)?

I can provide more detail if it is helpful...

Thanks, Joey

Reply to
Joseph

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