Field-Programmable Gate Arrays

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Question about TCL command of modelsim

Hi, I do not understand the .tcl command, which is issued by Matlab Simulink to run Modelsim in HDL Coder. More specifi...
5 comments posted 13yrs
posted by rxjwg98
5 comments posted 13yrs posted by rxjwg98

viewing old aldec/xilinx foundation schematics

Hi, we have a very old project where schematic entry was used using the xil inx foundation 3 software with aldec schema...
2 comments posted 13yrs
posted by tacowalstra
2 comments posted 13yrs posted by tacowalstra

ST Micro GOSPL open source EDA tools?

Hi, around 2004, there was an effort by ST Micro to enter the FPGA market. In t his context, ST published a set of open...
0 comments posted 13yrs
posted by cuby.engel
0 comments posted 13yrs posted by cuby.engel

pci express reference clock step down

A PCI Express master (a "root complex") generates a 100 MHz reference clock to target devices. In some cases that we've...
2 comments posted 13yrs
posted by jlarkin
2 comments posted 13yrs posted by jlarkin

Real Time Protocol - RTP using FPGA

in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I wa...
3 comments posted 13yrs
posted by emrith
3 comments posted 13yrs posted by emrith

Xilinx XC3S400 reproducibility madness

Hello all I am facing a strange problem: I am not able to generate a properly working bitstream from an original set of...
7 comments posted 13yrs
posted by nmatringe
7 comments posted 13yrs posted by nmatringe

Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the ma...
2 comments posted 13yrs
posted by gnuarm
2 comments posted 13yrs posted by gnuarm

TMDS CML PCB

Hello, I have problem with understanding differential nature of DC coupled CML pair in TDMS (DVI, HDMI). In DC coupled...
2 comments posted 13yrs
posted by 3827
2 comments posted 13yrs posted by 3827

Using LVDS Input for Delta Sigma ADC

I found an app note on the Lattice site about using the LVDS input as the input comparator. My design is very low power...
6 comments posted 13yrs
posted by gnuarm
6 comments posted 13yrs posted by gnuarm

Altera delivery

We are seeing huge leadtimes on Altera FPGAs, specifically Arria II GX65 and 95. Numbers like 20 weeks and worse. Is th...
18 comments posted 13yrs
posted by jjlarkin
18 comments posted 13yrs posted by jjlarkin