What the advantages and disadvantages between distributed arithmetic and seial-parallel based MAC?

Question

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient architect ures for the MAC. One is distributed arithmetic, while the other is serial- parallel multiplication based. I know that DA normally is for one of the mu ltiplicant is constant. The serial-parallel mulication has no such requirem ent. When one of the multiplicant is constant, it can save some logic gates indeed. Both methods process one bit with one clock cycle. What the differ ences are for these two architectures?

Thanks.

Tim Wescott · Accepted Answer

Define "efficient". Operations per clock? Number of gates? Shortness of pipeline? Joules per operation?

To my knowledge, most FPGAs these days come with built-in, hard-coded MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA without hitting one). So, by many definitions, using one is "most efficient" if you have such an FPGA.

While I freely admit that I don't have the knowledge base to answer your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I strongly suspect that the real answer is that you need to investigate each one, and decide which best matches _your_ idea of "efficient".

Les Cargill · Answer

All the fun part is done in the magjack anyway. An Ethernet MAC is mostly tedium. -- Les Cargill

Tim Wescott · Answer

I hope you realize that I meant "multiply and accumulate", not "media access" or whatever MAC means to Ethernet. At any rate, count my leg as pulled.

Les Cargill · Answer

I went halfway through the thread before I realized it *was* a "Multiply and Acucmulate", which was the inspiration for the joke. We're running out of TLAs. -- Les Cargill

What the advantages and disadvantages between distributed arithmetic and seial-parallel based MAC?

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