Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)


I want to verify if it is possible to use the CE10 to replace the CE15. Som e pins that are GND or VCCIO/VCCINT/VCCA on the CE15 are IOs on the CE10. T he GNDs are not a problem. But pins connected to VCCINT are as 1.2V are in the undefined input voltage range (VCCIOs are 3.15V in my design.) I will n ot define these pins in my project unless I have to.

Another concern is that a pin that was used as clock input (100MHz) is CLK1

0 on the CE15 is a regular IO on the CE10. Could that be an issue?

Thanks for your inputs.

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You may be able to select an IO standard for the pin(s) that will be connec ted to VCCINT, such that 1.2V is safely within a valid input range. That wo uld likely require defining those pins in order to constrain them.

The clock should only be an issue if you have any intputs or outputs for wh ich timing relative to that clock input is critical (e.g. if the FPGA commu nicates with some other device that shares the same board-level clock signa l, or buffered versions thereof).


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