Field-Programmable Gate Arrays

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LCD Interface

Hi, I've been struggeling with a long standing problem driving a 320x240 graphic LCD display. I've been using a LCD mod...
6 comments posted 21yrs
posted by pierre.devos
6 comments posted 21yrs posted by pierre.devos

Gated clock for FPGA (verilog)???

Hello, I want to implemented a gated clock signal that is active for only a certain period. What is the best way? I did...
5 comments posted 21yrs
posted by yijun_lily
5 comments posted 21yrs posted by yijun_lily

Quick Xilinx KCPSM3 with verilog question.

Does anyone actually believe that KCPSM stands for Constant(k) Coded Programmable State Machine, as opposed to Ken Chap...
0 comments posted 21yrs
posted by pm940
0 comments posted 21yrs posted by pm940

UDP problems with Xilinx EDK 7.1

Hi All, I am having some problems using UDP LwIP calls in EDK7.1. Let me give some details. I am trying to create an Et...
1 comments posted 21yrs
posted by jswestra77
1 comments posted 21yrs posted by jswestra77

Fine grain vs. Coarse Grain Architectures

Hello everybody, What are the main advantages of Fine Grain versus Coarse Grain Architecures and vice-versa. Thanks.
5 comments posted 21yrs
posted by alisson.brito
5 comments posted 21yrs posted by alisson.brito

Embedded Processors/Serdes

Does anyone know of another FPGA (other than Virtex series from Xilinx) that has an embedded processor comparable to the...
9 comments posted 21yrs
posted by blah
9 comments posted 21yrs posted by blah

openrisc, jp1 jtag debug utility

i've worked thru all of the openrisc HW and SW steps. everything went well, or at leas seemed to. however, when i start...
4 comments posted 21yrs
posted by jeff.murphy
4 comments posted 21yrs posted by jeff.murphy

8087 co-processor

hi, im wondering whether there is a point in using 8087 Math Co-Processor in this FPGA Age? CMOS
3 comments posted 21yrs
posted by manusha
3 comments posted 21yrs posted by manusha

Array of slope A/Ds in FPGA?

Hi. I need to digitize an array of signals (24) with minimum 8-bit resolution, with < 2ms conversion time. Signals are...
17 comments posted 21yrs
posted by localhost
17 comments posted 21yrs posted by localhost

JTAG conifguration via USB

Hi group, I've built an IO board [1] for an FPGA module to be used in a DSP lab at the university. The idea is to use U...
0 comments posted 21yrs
posted by mschoebe
0 comments posted 21yrs posted by mschoebe

Checking the PCI master implemented in FPGA

Hi All, I have implemented a AHB-PCI IP in the virtex2pro FPGA. While accessing through ARM JTAG AMBA side is okay , bu...
0 comments posted 21yrs
posted by praveenkumar1979
0 comments posted 21yrs posted by praveenkumar1979

Monitor the internal signal of EDF using chipscope

Hello guys, I am integrating a IP which is available has EDF netlist format. I am facing some problem in this IP. So in...
0 comments posted 21yrs
posted by stud_lang_jap
0 comments posted 21yrs posted by stud_lang_jap