Currently I am transfering 9 bits of data from one Spartan 3 to another using 9 LVCMOS25 lines. A 30 MHz clock supplies a source clock or "data strobe" which I have brough into a DCM for signal alignment.
I would like to serialize this to free up some of the 9 lines for other uses. Some of the Xilinx App notes seem a little too high end. What can I do with just flops and muxes? What sort of bandwidth can I get? I would like to keep my BRAMs free.
You mean you want to build a SERDES out of flops & muxes?
That's difficult to do well, but if you just want to serialize the data and you can still send the clock over a separate line, then it's not a problem.
The Clock and Data Recovery (CDR) in a SERDES is tough to do in regular FPGA resources.
You can use LVDS do transfer data at a much higher rate. I'm running a
4 bit double data rate bus between two Spartan3s at 133MHz DDR (266Mnibbles/second), the bus runs over a ribbon cable and uses a source synchronous clock on each direction. You do do something similar with a narrower bus.
I just built a SERDES interface (Cyclone) out of logic. It is comprised of a PLL, DDIO (gives you the choice to sample on the falling or rising edge of the fast clock), shift register, and an output flop. The key is to be cognizant of internal FPGA delays, that is, if you're not using an FPGA that has fast perimeter silicon. Care has to be taken of where to place the various elements of the design. You may have to massage the design after the fitter is done. This can be a tricky task if your FPGA design is using alot of LE's.
My data was being serialized at 266MHz (3.76nsec); so the data can easily get misaligned if you're not careful. Cyclone doesn't have any fast SERDES silicon so I was forced to do this with regular FPGA resources. Furthermore, my design wasn't doing anything much beyond derserializing data and sending it out in parallel form; which made it easier to control routing paths and prop delays.
Board trace lengths are important, too. Any skew between the data and the clock could pose a problem.
Yes, I should have been more explicit in my answer - a single frequency SERDES can be done if you take Rob's advice, however, you also have to be cognizant of jitter, of error correction (how are you going to deal with a 35MHz noise burst in the middle of your data?) etc. If you can, I'd still advise you to use a source synchronous clock.
Where would the 35 MHz noise burst in the middle of the data come from, and why? What do you think it would look like?
Brad, you didn't mention exactly how the clocks are fed to/between the two FPGA's, nor how far apart the devices are. Considering you are talking about 9 bits x 30 MHz, it sounds like you're needing to transfer at max, 270 Mbits/sec. As long as your traces are nice and short, you should be able to cut this down to a single LVCMOS25 net (or single LVDS diff pair if you want some added security and if you have a diff pair set up between the two devices).
You may want to compare the effort and complexity of a bit aligner in the receiver as opposed to chewing up one more pin for a bit alignment sync pulse.
It's a six layer board, I don't know where the noise would come from. Like I said, I'm looking for a low-end solution here.
I guess it's a synchonous source type clock, although, know that this is the first that I am using these terms. So the 30MHz is routed to a pin, travels about an inch, to the global clock input of the destination Spartan. I put a DCM there, with a fixed delay now at about 4ns, to allow some setup time for the parallel data that I have now.
That's right.
I did pair up the lines, in case I wanted to do just that. So what performance increase could I expect there, ballpark? Do I need to add termination resistor to do this?
Seems to me that the source clock should be an adequate sync pulse. No?
Sorry, I'm still not clear. Do I understand you that you have a single
30 MHz clock feeding both FPGA's, routed in a daisy-chain fashion, with the second leg of the daisy-chain being only 1" long (those devices must be really close together)? On both devices does the clock go into the GCLK input?
If you do a Google search on something like "lvds advantages cmos OR lvcmos", you'll get a number of hits, including an appnote from one of my more favorite companies:
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Note that they list CMOS (including LVCMOS) as having a max speed of "less than 100 Mbps". This is really, really conservative. We have a few LVCMOS25 busses on some of our boards running at over 300 MHz. It's all dependant on distance and slew rate.
LVDS requires a 100 ohm termination at the receiver. If memory serves, the S3 doesn't have 100 ohm on-chip termination, so yes, you'd need to put one as close to the pins as possible.
When you take a byte (or 9 bits, in your case) and send it one after another in a serial fashion, how are you going to know where the first byte ends and the second byte begins? There are a VERY large number of ways to do this.
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