Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

OSERDES as delay regulator e.g. Artix 7

Dear all, as some of you know that the Artix 7 has no ODELAY so I can't handle my delays for the output. But there is a...
0 comments posted 13yrs
posted by awelker
0 comments posted 13yrs posted by awelker

platform cable usb II and efuses on spartan-6

has anyone managed to do anything with efuses on spartan-6? I expected to use an old parallel cable since I usually hav...
0 comments posted 13yrs
posted by langwadt
0 comments posted 13yrs posted by langwadt

Aldec Active-HDL - No Default Binding Errors

I'm getting some errors when I try to compile my design in Aldec's Active-H DL. # Warning: ELAB1_0026: BITADJ128.bde(BI...
0 comments posted 13yrs
posted by trayres
0 comments posted 13yrs posted by trayres

Vivado - Pack I/O Registers?

Hello, Has anyone found the option in Vivado that controls I/O register packing? ISE has a single implementation option...
7 comments posted 13yrs
posted by padudle
7 comments posted 13yrs posted by padudle

Idea Hunt, FPGA + ARM Cortex-M3

I aim to demonstrate the need for FPGAs as compared to MPUs like (e.g. ARM Cortex-M3 based from TI/ST) in doing process...
3 comments posted 13yrs
posted by shanjitsingh
3 comments posted 13yrs posted by shanjitsingh

Using CAN on Zynq

Hello, might not be a real FPGA question, but I hope that some of you doing not only the hardware part but also working...
2 comments posted 13yrs
posted by hj.oertel
2 comments posted 13yrs posted by hj.oertel

Sometimes I Just Don't Get the Tools

I've learned to use Active HDL some time ago and never had too much trouble with it. But now it is not letting me use t...
8 comments posted 13yrs
posted by gnuarm
8 comments posted 13yrs posted by gnuarm

ip core implementation on fpga

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design. ERROR:P...
1 comments posted 13yrs
posted by dpk.losser
1 comments posted 13yrs posted by dpk.losser

JTAG, CONF_DONE failed to go high in device 1.

This is actually a re-post of my thread on alteraforum.com. ( www.alteraforum.com/forum/showthread.php?t=39255&p=161811...
2 comments posted 13yrs
posted by 4074
2 comments posted 13yrs posted by 4074

implementation of 8051 ip core on fpga

i am getting these errors can anybody help!! ERROR:HDLCompilers:27 - "../../Documents and Settings/deepak/Desktop/8051/...
3 comments posted 13yrs
posted by dpk.losser
3 comments posted 13yrs posted by dpk.losser

TTA-based Co-design Environment (TCE) v1.7 released

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport...
0 comments posted 13yrs
posted by pekka.jaaskelainen
0 comments posted 13yrs posted by pekka.jaaskelainen