Latest threads in Field-Programmable Gate Arrays

CFP - EuroMPI Workshop: PBio 2013 (proceedings published by ACM DL) + Special Issue in Journal PARCO (IF: 1.311, Q1)

Call for Papers --- EuroMPI Workshop: International Workshop on Parallelism in Bioinformatics ( proceedings published b...

0 13yrs

mavega

0 13yrs mavega

ModelSim version numbers

Does anyone know why ModelSim version numbers skipped from 6.6 to 10, missing out 7, 8,and 9? Thanks in anticipation. --...

2 13yrs

2161

2 13yrs 2161

OSERDES as delay regulator e.g. Artix 7

Dear all, as some of you know that the Artix 7 has no ODELAY so I can't handle my delays for the output. But there is a...

0 13yrs

awelker

0 13yrs awelker

platform cable usb II and efuses on spartan-6

has anyone managed to do anything with efuses on spartan-6? I expected to use an old parallel cable since I usually hav...

0 13yrs

langwadt

0 13yrs langwadt

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea The Emb...

0 13yrs

jeonggun.Lee

0 13yrs jeonggun.Lee

Aldec Active-HDL - No Default Binding Errors

I'm getting some errors when I try to compile my design in Aldec's Active-H DL. # Warning: ELAB1_0026: BITADJ128.bde(BI...

0 13yrs

trayres

0 13yrs trayres

arm cortex M0 ds and legacy spartan 3E 3A 3ADSP starter kits

hi folks, I am investigating for edu. purposes arm cortex M0 "design start edition" in legacy spartan3E1600 or 3adsp180...

1 13yrs

rponsard

1 13yrs rponsard

Vivado - Pack I/O Registers?

Hello, Has anyone found the option in Vivado that controls I/O register packing? ISE has a single implementation option...

7 13yrs

padudle

7 13yrs padudle

Idea Hunt, FPGA + ARM Cortex-M3

I aim to demonstrate the need for FPGAs as compared to MPUs like (e.g. ARM Cortex-M3 based from TI/ST) in doing process...

3 13yrs

shanjitsingh

3 13yrs shanjitsingh

Using CAN on Zynq

Hello, might not be a real FPGA question, but I hope that some of you doing not only the hardware part but also working...

2 13yrs

hj.oertel

2 13yrs hj.oertel

Sometimes I Just Don't Get the Tools

I've learned to use Active HDL some time ago and never had too much trouble with it. But now it is not letting me use t...

8 13yrs

gnuarm

8 13yrs gnuarm

ip core implementation on fpga

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design. ERROR:P...

1 13yrs

dpk.losser

1 13yrs dpk.losser

JTAG, CONF_DONE failed to go high in device 1.

This is actually a re-post of my thread on alteraforum.com. ( www.alteraforum.com/forum/showthread.php?t=39255&p=161811...

2 13yrs

4074

2 13yrs 4074

implementation of 8051 ip core on fpga

i am getting these errors can anybody help!! ERROR:HDLCompilers:27 - "../../Documents and Settings/deepak/Desktop/8051/...

3 13yrs

dpk.losser

3 13yrs dpk.losser

Re: i've used a verilog ip core of 8051...plz someone tell me what should i put in the "top module" feild provided..its showing error.plz its urgent someone help.

Absolutely nothing, because he mistook the title for the text. I'm not going to even attempt to read the post that you...

1 13yrs

tim

1 13yrs tim

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