Latest threads in Field-Programmable Gate Arrays

TTA-based Co-design Environment (TCE) v1.7 released

TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport...

0 13yrs

pekka.jaaskelainen

0 13yrs pekka.jaaskelainen

full tcp offload solution with tcp session setup/teardown support

Hello, I am searching for a fpga accelerated ethernet card solution for facing tcp sessions before OS. The solution sho...

10 13yrs

oguzyilmazlist

10 13yrs oguzyilmazlist

Button clock

Hi to everyone! This is my first message here so first of all thanks to everyone to let me post here! I have a homework...

5 13yrs

4060

5 13yrs 4060

IP core implementation of multiplier on FPGA Spartan 3e

i was tryin to implement an ip core of multiplier on fpga spartan 3e,but in the synthesysing process it is showing some...

3 13yrs

dpk.losser

3 13yrs dpk.losser

Data output constraint

Hello, I asked some time ago for constraints learning materials. It is hard to learn only with reading, I think I shoul...

6 13yrs

4030

6 13yrs 4030

need help in writing VHDL code for modified booths algorithm using wallace tree

hi i want to write a vhdl code for booth modified radix4 algorithm using wallace tree(3:2) and need help in this.. pleas...

0 13yrs

kishore.devesh

0 13yrs kishore.devesh

Combination loops and false paths

I creating an FPGA implementation of a old DEC PDP-10 (KS-10, specifically) Mainframe Computer. Why? Because I always w...

18 13yrs

radioengr

18 13yrs radioengr

is this multicycle?

Hi all, A counter runs on system clock, counting from 0~95 in steps of 1. every 3 counts, registers for two signals are...

9 13yrs

3619

9 13yrs 3619

Do you have any BROKEN Xilinx Platform Cable Usb or II

Hi, I need this because of the stupid bureoacracy of my workplace. People in Turkey or USA are wanted. Thanks in advance...

0 13yrs

eneserdin

0 13yrs eneserdin

Quartus 12.1 Web Edition in 64-bit Linux - in System Sources and Probes do not work

Hi, I've installed the Quartus II 12.1 Web Edition for my students in 64-bit Linux machine, and I've found, that in Sys...

1 13yrs

wzab01

1 13yrs wzab01

FPGA board with SD card slot (code test)

Hello, I'm looking for some kind person who could test my SD card controller. Board with SD card slot with 4 data pins...

2 13yrs

4030

2 13yrs 4030

Lattice iCECube2 for iCE40 Devices

How many have used the iCECube2 tool? I am just getting started with it and it seems to be less than optimal. It uses S...

4 13yrs

gnuarm

4 13yrs gnuarm

Constraints learning materials

Hello, I'm new in FPGA world. I read some VHDL books and I can create not much advanced, but working projects. Most of...

3 13yrs

4030

3 13yrs 4030

MIG help (Virtex-6)

Hi I have created a controller for DDR3 with the MIG. The MIG output folders are example_design and user_design. accord...

1 13yrs

2787

1 13yrs 2787

Chisel as alternative HDL

Hi all, started to look into alternatives to Verilog and VHDL and stumbled over chisel from UCB: http://chisel.eecs.ber...

52 13yrs

martin

52 13yrs martin

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