Bus master DMA and cache coherency

Hello,

Hopefully these groups are appropriate for this quesiton, apologies if not.

I've designed a PCI card that does data capture, along with a driver module for Linux 2.4. It all seems to work fine, BUT I have one nagging doubt regarding the DMA performance.

I've implemented a data-aware bus master DMA on the PCI interface FPGA, i.e. the PCI card is initialised to transfer a v.large amount of data (upto

512Mbytes). When data is available the card initiates the transfer into the allocated memory location. The memory is then mmap'd into user space, where the user app/driver can interogate the PCI card to find out how much data has been transferred, and process it accordingly. So far so good, all seems to work.

The doubt I have is regarding cache paging. Scenario - 2300 bytes of data are received by the PCI card and transferred into the bottom of the memory area. The application/driver detects this transfer and starts processing the data. This will cause the memory page to be copied into the processor cache. While the app is processing this data more (e.g.3400bytes) data arrives in the PCI card and is transferred into memory. When the application has processed the first block of data, it interrogates the PCI card and detects the new data. When it goes to process it, it looks for the data at the end of the first block, BUT and here's the doubt, is there any reason to believe that the page in cache will have been invalidated and reloaded when the 2nd block of data was transferred by the PCI cards DMA action ? Or will the application be looking at the "old" data that was in the unused part of the page when it was first copied into cache ?

At the moment I've designed round this concern, by modifying the data handover protocol and ensuring the driver module only hands data over in

4096 byte blocks (Linux 2.4 default page size).

The target platforms are PCs using standard Intel chipsets.

Any hints appreciated.

Many Thanks

Gordon

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