Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

9bit vga with resistors.

Don't know if it fits here or not, but since I'm using a fpga I gues it does I've got a spartan-3 starter board and got...
1 comments posted 20yrs
posted by miti0200
1 comments posted 20yrs posted by miti0200

ISE 7.1i installing issues on Windows XP Pro Sp2.

Hello, Iam having trouble installing ISE 7.1i on brand new Dell PC. The PC just reboots midway through the installation...
0 comments posted 20yrs
posted by brijesh_xyz
0 comments posted 20yrs posted by brijesh_xyz

Xilinx WebPack and command line

I wonder if there is a posibility to do Xilinx fpga synthesis and implementation from command line on WindowsXP platfor...
8 comments posted 20yrs
posted by norvilis
8 comments posted 20yrs posted by norvilis

FPGA behaviour when its used resource is >90% ?

Hi, We are using Xilinx Spartan2E in our platform and so far functioning of every logical cores was looking good. Today...
8 comments posted 20yrs
posted by kkumar
8 comments posted 20yrs posted by kkumar

DDR constraints in Xilinx/UCF, Synplicity?

HELP! How to constrain source-synchronous DDR inputs in Xilinx? In Synplify Pro? Double Data Rate input scenario: CLK =...
3 comments posted 20yrs
posted by jjohnson
3 comments posted 20yrs posted by jjohnson

Raggedstone1

For those of you asking for details of Raggedstone1 the initial draft spec is here http://www.enterpoint.co.uk/moelbryn...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

matrix inversion in hardware

Hello all, I've recently been examining methods for acceleration of matrix inversion... does anyone know of any hardwar...
1 comments posted 20yrs
posted by rafaelcns
1 comments posted 20yrs posted by rafaelcns

Xilinx PLB IPIF Master

Hello: Has anyone actually gotten the master functionality in the PLB IPIF to work correctly? I have been making slave...
3 comments posted 20yrs
posted by emh203
3 comments posted 20yrs posted by emh203

Verification using Chipscope

Hi All Is it possible to send test vectors through Chipscope to the FPGA via JTAG and then get outputs to verify the fun...
1 comments posted 20yrs
posted by thakkar.anuja
1 comments posted 20yrs posted by thakkar.anuja

Altera Gate Delay Simulation

I am doing some work targeted to StratixGX family for me RTL or gate delay simulation is a must. Can i do a post synthe...
5 comments posted 20yrs
posted by kedarpapte
5 comments posted 20yrs posted by kedarpapte

FSM with High load on clock signal

Hallo, I have made a clock divider (1 MHz) with a counter connected to system clock (50 MHz). This counter has a thresh...
9 comments posted 20yrs
posted by marcotoschi
9 comments posted 20yrs posted by marcotoschi