Hello
Has anyone here had experience with interrupt latency in a PowerPC block in a VirtexII Pro? I did a simple experiment where I setup a PowerPC core where the critical interrupt input is always raised (just tied it to net_vcc in the .mhs file). I then registered a very simple interrupt handler:
void MyIrqA(void * arg) {
i = MYIP; // read a generic register on the PLB Bus
}with built Xilinx Functions:
XExc_RegisterHandler(XEXC_ID_CRITICAL_INT, (XExceptionHandler)MyIrqA, (void *)0);
and then enabled the interrupt with:
XExc_mEnableExceptions(XEXC_CRITICAL);
I then monitor a bus read signal for my generic register to see how often it occurrs. The PLB bus and PowerPC is being clocked at 100MHz on a Digilent VirtexII Pro development board.
To my surprise, there is almost 10uS between reads! I know this isn't a PLB bus issue, I can do multiple reads in the interrupt route and the read pulses are within a few bus cycles of each other.
Is there anythign I can do to help this? What in the world is Xilinx doing in their BSP to save context that takes 10uS with a 100MHz clock period?
-Eli Hughes