Field-Programmable Gate Arrays

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Inferring DSP48 PATTERNDETECT and ACIN/ACOUT cascade

I'm using Synplify and trying to infer some DSP designs into DSP48s. Somet imes it works well, but it's sporadic. I'd l...
0 comments posted 13yrs
posted by kevin.neilson
0 comments posted 13yrs posted by kevin.neilson

ASIC prototyping question for Xilinx V7 2000

(1) I need to prototype Arm A5 processor in Xilinx V7 2000 FPGA. A5 has AX I bus and Xilinx supports DDR3 Controller+AX...
0 comments posted 13yrs
posted by cpandya
0 comments posted 13yrs posted by cpandya

Using Quartus II without GUI

Dear All, Is there a tutorial for using Quartus II without the GUI? Ie. how to create a new project, how to configure P...
4 comments posted 13yrs
posted by jmarin
4 comments posted 13yrs posted by jmarin

The Raspberry Pi JTAG programmer

The Raspberry Pi JTAG programmer: http://panteltje.com/panteltje/raspberri_pi/
1 comments posted 13yrs
posted by pNaonStpealmtje
1 comments posted 13yrs posted by pNaonStpealmtje

Farnell increased price on Spartan 6

http://alturl.com/4dtfw Price went from 17 EUR to 25 EUR Haven't checked other ICs, I'm only interested in this one.
2 comments posted 13yrs
posted by aleksazr
2 comments posted 13yrs posted by aleksazr

EPROM programmer erase

(Sorry, this is a bit off topic, but I do use this to load bitfiles into FPGAs.) I have a Xeltek Superpro/Z eprom progr...
2 comments posted 13yrs
posted by elson
2 comments posted 13yrs posted by elson

IP for SDIO serial port

I have been looking for an SDIO serial port. A single chip would work as well. SDIO async serial port Txd, Rxd, CTS, RTS...
2 comments posted 13yrs
posted by hamilton
2 comments posted 13yrs posted by hamilton

Xilinx XST and initializing block RAMs

Hi all, I'm using XST 14.2 and trying to use block RAMs to store constant data (i.e. as ROMs) for program code that wil...
11 comments posted 13yrs
posted by chead
11 comments posted 13yrs posted by chead

Experience with Tektronix's FPGAview

Folks, Anyone can share their experience with the Tek's FPGAview? + Go ahead buy it + Wait for updates + Don't bother Th...
0 comments posted 13yrs
posted by parekhsanjayh
0 comments posted 13yrs posted by parekhsanjayh

about the always block in verilog

always @(negedge nrst or posedge PCLK or negedge begin) begin ... end So,how can i determine what event does really happ...
20 comments posted 13yrs
posted by zydgyy
20 comments posted 13yrs posted by zydgyy

Spartan 3E Output Verification

Hi!! My Task: 1.I need to implement an INTEL 8051 core (Verilog) into a Xilinx Spartan 3E (xcs3500e) board. 2. After im...
0 comments posted 13yrs
posted by dravid.thunder
0 comments posted 13yrs posted by dravid.thunder

Help with .mem and .bmm file generation

Hi.. am supposed to implement a 8051 open core into a spartan 3e board and verify the implementation with led blink pro...
3 comments posted 13yrs
posted by venkatesh27989
3 comments posted 13yrs posted by venkatesh27989

ModelSim version numbers

Does anyone know why ModelSim version numbers skipped from 6.6 to 10, missing out 7, 8,and 9? Thanks in anticipation. --...
2 comments posted 13yrs
posted by 2161
2 comments posted 13yrs posted by 2161