Inferring DSP48 PATTERNDETECT and ACIN/ACOUT cascade

I'm using Synplify and trying to infer some DSP designs into DSP48s. Somet imes it works well, but it's sporadic. I'd like the DSP48s to be cascaded using the ACOUT/ACIN dedicated paths, and sometimes this works, but in othe r designs it puts the delay lines in fabric. It seems to be very sensitive to the "syn_retiming" attribute on certain nets, even though this doesn't seem to be related to retiming at all. I'm also doing convergent rounding and want my "tie detector" to be pulled into the DSP48's PATTERNDETECT, whi ch, again, works sometimes and sometimes doesn't, even in code written almo st exactly the same in a different module. (Using VHDL.) And sometimes Sy nplify will move all the registers around and put some in fabric. I'll hav e A1, A2, B1, B2, M, and P registers, and Synplify will pull A1 into the fa bric, A2 into A1, M into A2, and then leave out the M register. Is there a ny good way to make it do what I want without instantiating DSP48s, which I 'd rather avoid?