Field-Programmable Gate Arrays

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RPM reference for xilinx

Hi all, I have a FIR filter which I would like to make a RPM of to see what all the fuss is about. But I don't know the...
3 comments posted 20yrs
posted by dontreplytothisaddy
3 comments posted 20yrs posted by dontreplytothisaddy

Avnet Technical Support Terrible!!!

I've got to say so far I have been extremely unhappy with Avnet's level of Technical Support. I purchased their Virtex-...
11 comments posted 20yrs
posted by chris
11 comments posted 20yrs posted by chris

EDK on Virtex4 FX using embedded ethernet MAC

Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK...
4 comments posted 20yrs
posted by padudle
4 comments posted 20yrs posted by padudle

EDK/ISE : unroutable design

Hi, I'm a Phd student using EDK (7.1i) in order to prototype a multiple processor system in a single chip. I have made...
6 comments posted 20yrs
posted by damez
6 comments posted 20yrs posted by damez

to write the driver for my own ip core

Hi All, I have writen an IP core which is used for implementing an algorithm. Now I have to write the driver for my IP...
5 comments posted 20yrs
posted by lnzhao
5 comments posted 20yrs posted by lnzhao

MAC Architectures

Jeorg's question on sci.electronics.design for an under $2 DSP chip got me to thinking: How are 1-cycle multipliers imp...
26 comments posted 20yrs
posted by tim
26 comments posted 20yrs posted by tim

Spartn 3 configuration failure

Hello, I am a newbie to the group and FPGAs in general. We have a board with XC3S1500 FPGA on it. We use the master ser...
2 comments posted 20yrs
posted by nithin.pal
2 comments posted 20yrs posted by nithin.pal

which is Low power FPGA?

Hi, Please advice me on low power FPGA available in the market. which is the low power consumption FPGA among Xilinx -...
11 comments posted 20yrs
posted by himassk
11 comments posted 20yrs posted by himassk

Implementation of 1024 point FFT in Actel FPGA

Hai, I want to do the main project as Implementation of 1024 point FFT in Actel FPGA.I have to find a new frequency ide...
3 comments posted 20yrs
posted by cisivakumar
3 comments posted 20yrs posted by cisivakumar

How to speed up the critical path (Xilinx)

Hi there, I would be happy about some suggestions on how I could start to make my design faster. My design is a process...
5 comments posted 20yrs
posted by starbugs
5 comments posted 20yrs posted by starbugs

WANTED: Contract Verilog Designer

We have an immediate requirement for a Verilog designer for a short-term (approx. 3 month) period. This job involves co...
0 comments posted 20yrs
posted by
0 comments posted 20yrs posted by

Webpack install yields "299" error

Neophyte looking for help installing webpack 7.1. Being a student has denied me access to webcase. Any insight would be...
0 comments posted 20yrs
posted by Eboy
0 comments posted 20yrs posted by Eboy

Xilinx USB cable

Today I had a talk with the representant of Xilinx in russia. He adviced me to use Parallel cable 4 and not USB cable b...
7 comments posted 20yrs
posted by taileb.mehdi
7 comments posted 20yrs posted by taileb.mehdi