hi,
how i can prevent netgen (ise7.1i) from renaming std_logic_vector ports like this
X1_CON(7 downto 0) -> X1_CON_0_Q, X1_CON_1_Q, X1_CON_2_Q, ....
any ideas ?
hi,
how i can prevent netgen (ise7.1i) from renaming std_logic_vector ports like this
X1_CON(7 downto 0) -> X1_CON_0_Q, X1_CON_1_Q, X1_CON_2_Q, ....
any ideas ?
-- Dr.-Ing. A. Wassatsch Max-Planck-Institut für Physik München
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