clock frequency after RTL synthesis vs PAR

Close. Before the above line, you probably need to add

NET "clk" TNM_NET = "clk";

Have fun,

Marc

yes i added of course as below. I find that 5% - 15% performance degradation before PAR and after PAR...

Wondering how to reduce the gap.... Thankyou.

--------V2pro NET "clk" LOC = "AJ15"; NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 6.608ns HIGH 50 %; NET "rst" LOC = "AE10" ; NET "out1" LOC = "AB4" ;

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With no information on what is failing timing, I can only make general suggestions: There are effort levels in PAR - have you played with those? Timing based mapping also makes a big difference. If those don't get you anywhere, you may need to reduce levels of logic.

Good luck,

Marc

Hi Pasacco, I take it that you are concerned about the performance degradation of the static timing analysis (STA) results before and after PAR. STA before PAR does not take into account the routing delays within the FPGA which typically account for half or less of the total delay. Pre-PAR STA would only take into account logic delays. So there will be some performace degrdation in post-PAR STA. (source : Constraints Guide

To minimize your routing penalty, read

Timing Closure - 6.1i 04/07/04 By Rhett Whatcott Senior Course Developer/Trainer Xilinx San Jose

available under TechXclusives on xilinx.com. That may help.

Kunal