I am sending an ethernet packet(64 bytes) from the fpga to the PC in order to test the ETHERNET PHY chip onboard. The interface from the fpga to the ethernet PHY for the data is 4 bits.
My PC mac address is 00-01-80-3F-6C-E6
a)So should i send the LSBs first like in this order, 6,E,C,6,F,3,0,8,1,0,0,0 or the MSBs first
b) I have installed ethereal software on my PC and i am unable to detect the ethernet packet in it. 1) I am pretty sure my CRC is wrong for whatever data i have, so can ethereal still detect even when crc is wrong?2)i used the scope , and i am able to see some data going from fpga to the ethernet PHY. But the nothing gets detected in the PC. What could be the reason?
One of the member in this group recommended not to see the data coming out of the ETHERNET phy , since its at 125 mhz and its not being detect correctly using a scope.3)Can anyone compute the crc check for whole ethernet packet for which my destination addres is as above? Data doesnt matter,it can be any value.?Source address also doesnt matter, since it is fpga mac address.
4) Can anyone guide me on hardware implementation of crc using vhdl