[xst]:clk information question

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i made a design for a LVDS input (with some tweaks) and the design is = working but i found this info warning in the syr and i was wondering why = i get this warning ... since all of the clks are generated by a DCM and = each clk has its own bufg ...

what happens is, the lvds clk is coming in on a BUFGDS input buffer and = goes to a DCM module, this DCM module has the DCM + all of the recovery = logic + all the other buffers for the feedback and output clks... so = every clk goes through a buffer but why do i get the following warning:

Clock Information:

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Tim Verstraete
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