Hi,
I've got a problem which has me stumped.
We've got a design that actually *runs* in real hardware. I'm in the process of adding the block to an existing testbench that contains other FPGAs.
In the new design (Cyclone II) is a PLL, input frequency 24MHz. I'm generating the clock input in the testbench (VHDL). Two output clocks are used, C1 & C2, both 112MHz (slight phase difference).
I've imported the .VHO output into the testbench, together with the cycloneii_atoms and cycloneii_components files. I should also add that the altera_mf & 220pack files are also in the project (for other modules).
But, when I simulate the design, C1 & C2 are driving 'X'. Looking inside the PLL, it's not locking. According to the doco, it should lock in (IIRC) 2-10 cycles - I'm simulatng for *thousands* of cycles. And the simulation resolution is set to 1ps. I've also tried eliminating the phase offset for C2.
Any ideas what I could be doing wrong? Anyone else had problems simulating cycloneii PLLs?
FWIW I've had no problems in the past with cycloneii pll simulation, although that project did *not* include altera_mf and 220pack files.
Regards, Mark