Hi,
We need to evaluate new CLB architectures for routing area and delay. In VPR how can I specify my CLB architecture accurately. In architecture file all I could find out was that we can change number of LUTs and their input size. But in our architectures apart from LUTs we also have some extra combinational modules. Is it possible for me to specify no of transistors that my CLB takes in VPR and then let VPR do placement and routing because that will give routing area and delay according to our architecture. If yes where should I do that. I feel that currently VPR finds out number of transistors of a CLB based on number of LUTs present but I was unable to figure out where does it use this information after going through the code.
Kindly help me if someone has gone through the code or has modified it.
Thanks and regards,