Having trouble Detecting ethernet packets using ethereal

Hello Everyone again,

This topic is troubling me for couple of weeks now. I want to get over this as quickly as possible. I am trying to transmit data from the virtex 4 LX fpga board to the PC using ethernet PHY and i am unable to detect any data on the PC. I have written a small state machine using vhdl which actually transmits the ethernet packet( dest MAC, Source MAC, length/type, data, fcs(Crc)] . I am sure that FCS is correct as i tested my code for sample ethernet packets and i got it right.

There is a sample bit file given with the evaluation board to me for testing the ethernet PHY.So when i download this bit file and in the cmd , when i say ping fpga(mac address) and i start the ethereal capture. I am able to see the data transfer to and from between fpga and mac. But if i dont ping it and just start capturing by clicking the capture, i am not able to detect anything except the ARP which is data transferred from PCs ip address to broadcast.

In my project i dont ping in the cmd because i didnt include any ip address in my vhdl code. So basically i am not able to detect anything in the ethereal except the ARP which is being transferred from PC to broadcast. The format of the ethernet frame i am using is Destination MAC ad, Source MAC, length/type, data, FCS(CRC) and i am not using any ip address or udp header in my ethernet frame in the vhdl code.

Probably the data is getting transferred on to the PC, but not able to capture it since, i am not pinging it. So how do we see what data is coming out from the PHY.

Please advice ?

Thanks Ashwin

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Ethereal has no problems showing non-IP packets when it catches them.

Are you sending the correct preamble and SFD ? Do you see the link blink on the PC whenever you send something ? Manually copy a static IP packet bit by bit in your VHDL code, and send that as a test packet. Compare your version with the sample bit file by looking at PHY signals with a scope.

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With a fast digital oscilloscope ?


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Rene Tschaggelar

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Aurelian Lazarut

Hi Arlet The format i used for the ethernet frame is this: WIth the least significand bit transferred first. I have a 4 bit interface from fpga to PHY so i will transfer least significand nibble of each byte every clock cycle.

7 bytes of x"55"; 1 byte of x"d5"; 6 bytes of dest MAC address 6 bytes of source MAC address DATA -- 40 bytes 4 bytes of FCS

What do you mean by static IP packet. Does it include preamble and CRC too? The PHY converts the data into MLT-3 signal which is like a sinusoid. Its hard to decode manually what data is being sent out.


Arlet wrote:

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Hi Ashwin,

What about the 8b/10b encoding, are you encapsulating your ethernet packets with the SOP, EOP and Carrier Extend as specified in the ieee 802.3 spec...

It's been a while but I seem to remember that in my case (my own tri-rate mac+2vp rocketIO+external sgmii SFP) I had to encapsulate the data you decribed as:



Also make sure you send IDLEs when you don't transmit your packet...


Ignacio U. Hernandez
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I. Ulises Hernandez

With the static IP packet, I mean that you try to send out exactly the same IP packet that your sample uses. Instead of implementing an entire IP stack, you could use Ethereal to capture a good packet, look at the hex dump, and copy it exactly in your VHDL code. Then repeatedly send out that packet.

If you don't see your packet on Ethereal, but you see the sample, there must be a difference. Put your scope probes between the PHY and the FPGA to watch the digital signals. Compare between the two. Check the preamble, bit order, timing, CRC.

Also, don't forget to pad your data if it's too short.

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or an optiview:

formatting link

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Mike Treseler

you may want to send a length field before the data field too.


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Simon Peacock

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