Modelsim Verification : Retain FSM state names

Hi, That would be more of a Q to your synthesis tool (which I'm not overly familiar with). However Modelsim has a nice "virtual bus" command/feature to do exactly what you wanted - check their doc.

HTH Ajeetha

I have designed using ISE 7.1. Is there a way to retain the state names (i.e. reset_state,idle_state,run_state)in the modelsim post place and route simulation? I find it more convienient to see the state names than the values of the chosen fsm encoding type.

In each FSM I include a special section of code that assigns an ASCII string with the name of the current state to a reg variable. I then display the reg variable in the Modelsim waveform viewer in ASCII format. This section of code is inside an 'ifdef statement that is visible to the simulation tool but not the synthesizer. In Verilog it'd look like this:

`ifdef synthesis `else //---- ASCII string code goes here `endif

Bob Perlman Cambrian Design Works

using ISE 7.1. Is there a way to retain the state names (i.e. reset_state,idle_state,run_state)in the modelsim post place and route simulation? I find it more convienient to see the state names than the values of the chosen fsm encoding type.

Modelsim will display variables of enumerated type by name. For example: main : process (clock, reset) is type RxState_t is ( IDLE, START, RECEIVE, STOP, FULL, ERR ); variable RxState_v : RxState_t; begin -- . . .

Then tell modelsim to: add wave /test_uart/dut/main/*

-- Mike Treseler

Bob, I also follow that in old Verilog. Thanks to SV, we have enums. However the OP asked about Post place-and-route sim, hence this trick won't help much. One needs to build equivalent signal names and enum mapping. I believe MTI's virtual bus fits the bill better.

Regards Ajeetha

My mistake--I missed the part about post-place-and-route.

Bob Perlman Cambrian Design Works

This can be done if you manually encode the state-machine and then in the testbench apply descriptive ASCII text to the state-machine states in a separate variable.

For instance, if you describe the following state-machine in your source code:

parameter START = 3'b0001; parameter WAIT = 3'b0010; parameter START_OVER = 3'b0100;

(* FSM_ENCODING="USER" *) reg [2:0] state = BEGIN;

always@(posedge CLK) begin if (RST) begin state >mapping. I believe MTI's virtual bus fits the bill better.